EDAC, MCE: Rework MCE injection

Add sysfs injection facilities for testing of the MCE decoding code.
Remove large parts of amd64_edac_dbg.c, as a result, which did only
NB MCE injection anyway and the new injection code supports that
functionality already.

Add an injection module so that MCE decoding code in production kernels
like those in RHEL and SLES can be tested.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

7 files changed, 203 insertions, 207 deletions

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 70bb350de996..3bb3a671baa0 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -39,7 +39,7 @@ config EDAC_DEBUG
           there're four debug levels (x=0,1,2,3 from low to high).
           Usually you should select 'N'.
 
- config EDAC_DECODE_MCE
+config EDAC_DECODE_MCE
         tristate "Decode MCEs in human-readable form (only on AMD for now)"
         depends on CPU_SUP_AMD && X86_MCE
         default y
@@ -51,6 +51,16 @@ config EDAC_DEBUG
           which occur really early upon boot, before the module infrastructure
           has been initialized.
 
+config EDAC_MCE_INJ
+        tristate "Simple MCE injection interface over /sysfs"
+        depends on EDAC_DECODE_MCE
+        default n
+        help
+          This is a simple interface to inject MCEs over /sysfs and test
+          the MCE decoding code in EDAC.
+
+          This is currently AMD-only.
+
 config EDAC_MM_EDAC
         tristate "Main Memory EDAC (Error Detection And Correction) reporting"
         help
@@ -72,7 +82,7 @@ config EDAC_AMD64
           Families of Memory Controllers (K8, F10h and F11h)
 
 config EDAC_AMD64_ERROR_INJECTION
-        bool "Sysfs Error Injection facilities"
+        bool "Sysfs HW Error injection facilities"
         depends on EDAC_AMD64
         help
           Recent Opterons (Family 10h and later) provide for Memory Error
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index ca6b1bb24ccc..5c38ad38f3a3 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -17,6 +17,8 @@ ifdef CONFIG_PCI
 edac_core-objs  += edac_pci.o edac_pci_sysfs.o
 endif
 
+obj-$(CONFIG_EDAC_MCE_INJ)              += mce_amd_inj.o
+
 obj-$(CONFIG_EDAC_DECODE_MCE)           += edac_mce_amd.o
 
 obj-$(CONFIG_EDAC_AMD76X)               += amd76x_edac.o
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 613b9381e71a..67d9ceb4b839 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -486,7 +486,7 @@ extern const char *ext_msgs[32];
 extern const char *htlink_msgs[8];
 
 #ifdef CONFIG_EDAC_DEBUG
-#define NUM_DBG_ATTRS 9
+#define NUM_DBG_ATTRS 5
 #else
 #define NUM_DBG_ATTRS 0
 #endif
diff --git a/drivers/edac/amd64_edac_dbg.c b/drivers/edac/amd64_edac_dbg.c
index f6d5695de5b6..e3562288f4ce 100644
--- a/drivers/edac/amd64_edac_dbg.c
+++ b/drivers/edac/amd64_edac_dbg.c
@@ -1,173 +1,16 @@
 #include "amd64_edac.h"
 
-/*
- * accept a hex value and store it into the virtual error register file, field:
- * nbeal and nbeah. Assume virtual error values have already been set for: NBSL,
- * NBSH and NBCFG. Then proceed to map the error values to a MC, CSROW and
- * CHANNEL
- */
-static ssize_t amd64_nbea_store(struct mem_ctl_info *mci, const char *data,
-                                size_t count)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u64 value;
-        int ret = 0;
-        struct mce m;
-
-        ret = strict_strtoull(data, 16, &value);
-        if (ret != -EINVAL) {
-                struct err_regs *regs = &pvt->ctl_error_info;
-
-                debugf0("received NBEA= 0x%llx\n", value);
-
-                /* place the value into the virtual error packet */
-                pvt->ctl_error_info.nbeal = (u32) value;
-                value >>= 32;
-                pvt->ctl_error_info.nbeah = (u32) value;
-
-                m.addr   = value;
-                m.status = regs->nbsl | ((u64)regs->nbsh << 32);
-
-                /* Process the Mapping request */
-                /* TODO: Add race prevention */
-                amd_decode_nb_mce(pvt->mc_node_id, &m, regs->nbcfg);
-
-                return count;
-        }
-        return ret;
+#define EDAC_DCT_ATTR_SHOW(reg)                                         \
+static ssize_t amd64_##reg##_show(struct mem_ctl_info *mci, char *data) \
+{                                                                       \
+        struct amd64_pvt *pvt = mci->pvt_info;                          \
+                return sprintf(data, "0x%016llx\n", (u64)pvt->reg);     \
 }
 
-/* display back what the last NBEA (MCA NB Address (MC4_ADDR)) was written */
-static ssize_t amd64_nbea_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u64 value;
-
-        value = pvt->ctl_error_info.nbeah;
-        value <<= 32;
-        value |= pvt->ctl_error_info.nbeal;
-
-        return sprintf(data, "%llx\n", value);
-}
-
-/* store the NBSL (MCA NB Status Low (MC4_STATUS)) value user desires */
-static ssize_t amd64_nbsl_store(struct mem_ctl_info *mci, const char *data,
-                                size_t count)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        unsigned long value;
-        int ret = 0;
-
-        ret = strict_strtoul(data, 16, &value);
-        if (ret != -EINVAL) {
-                debugf0("received NBSL= 0x%lx\n", value);
-
-                pvt->ctl_error_info.nbsl = (u32) value;
-
-                return count;
-        }
-        return ret;
-}
-
-/* display back what the last NBSL value written */
-static ssize_t amd64_nbsl_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u32 value;
-
-        value = pvt->ctl_error_info.nbsl;
-
-        return sprintf(data, "%x\n", value);
-}
-
-/* store the NBSH (MCA NB Status High) value user desires */
-static ssize_t amd64_nbsh_store(struct mem_ctl_info *mci, const char *data,
-                                size_t count)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        unsigned long value;
-        int ret = 0;
-
-        ret = strict_strtoul(data, 16, &value);
-        if (ret != -EINVAL) {
-                debugf0("received NBSH= 0x%lx\n", value);
-
-                pvt->ctl_error_info.nbsh = (u32) value;
-
-                return count;
-        }
-        return ret;
-}
-
-/* display back what the last NBSH value written */
-static ssize_t amd64_nbsh_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u32 value;
+EDAC_DCT_ATTR_SHOW(dhar);
+EDAC_DCT_ATTR_SHOW(dbam0);
+EDAC_DCT_ATTR_SHOW(top_mem);
+EDAC_DCT_ATTR_SHOW(top_mem2);