diff options
| author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2007-11-01 08:51:23 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-11-02 12:13:48 -0400 |
| commit | 9aa4cc11b22ec447b42c5df03fdab5eb748971e2 (patch) | |
| tree | 9547849f3716ca354d4d4dea4691dd71c737ba40 | |
| parent | db0c19e1a6abd9a9bdbf3ffbabc1e8e4995cb462 (diff) | |
[MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | include/asm-mips/mach-cobalt/irq.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h index 179d0e850b59..57c8c9ac5851 100644 --- a/include/asm-mips/mach-cobalt/irq.h +++ b/include/asm-mips/mach-cobalt/irq.h | |||
| @@ -35,7 +35,7 @@ | |||
| 35 | * 4 - ethernet | 35 | * 4 - ethernet |
| 36 | * 5 - 16550 UART | 36 | * 5 - 16550 UART |
| 37 | * 6 - cascade i8259 | 37 | * 6 - cascade i8259 |
| 38 | * 7 - CP0 counter (unused) | 38 | * 7 - CP0 counter |
| 39 | */ | 39 | */ |
| 40 | #define MIPS_CPU_IRQ_BASE 16 | 40 | #define MIPS_CPU_IRQ_BASE 16 |
| 41 | 41 | ||
| @@ -48,7 +48,6 @@ | |||
| 48 | #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) | 48 | #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) |
| 49 | #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) | 49 | #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) |
| 50 | 50 | ||
| 51 | |||
| 52 | #define GT641XX_IRQ_BASE 24 | 51 | #define GT641XX_IRQ_BASE 24 |
| 53 | 52 | ||
| 54 | #include <asm/irq_gt641xx.h> | 53 | #include <asm/irq_gt641xx.h> |