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authorBenoit Cousson <b-cousson@ti.com>2011-07-09 22:42:11 -0400
committerPaul Walmsley <paul@pwsan.com>2011-07-09 22:42:11 -0400
commit9a2a3603cf1c57ed21adb045a771405ab27335c1 (patch)
tree3ca824c6b3aebdd39da936dfc92c13d6d708768c
parent6349b96b439515e1100cd98f27ff55a262f558a3 (diff)
OMAP4: powerdomain data: Fix core mem states and missing cefuse flag
Since ES2.0, the core ocmram does not support a different state than the main power domain anymore during both ON and RET power domain state. Since PM is not supported at all in ES1.0, update the common structure. LOWPOWERSTATECHANGE is supported by the cefuse power domain but the flag was missing. Add the PWRDM_HAS_LOWPOWERSTATECHANGE in flags field. Update the TI copyright date to 2011. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> [paul@pwsan.com: moved the indentation changes to a different patch set] Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index c4222c7036a5..631e45258de1 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 Power domains framework 2 * OMAP4 Power domains framework
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2009-2011 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
@@ -41,14 +41,14 @@ static struct powerdomain core_44xx_pwrdm = {
41 .banks = 5, 41 .banks = 5,
42 .pwrsts_mem_ret = { 42 .pwrsts_mem_ret = {
43 [0] = PWRSTS_OFF, /* core_nret_bank */ 43 [0] = PWRSTS_OFF, /* core_nret_bank */
44 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 44 [1] = PWRSTS_RET, /* core_ocmram */
45 [2] = PWRSTS_RET, /* core_other_bank */ 45 [2] = PWRSTS_RET, /* core_other_bank */
46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ 46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */ 47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */
48 }, 48 },
49 .pwrsts_mem_on = { 49 .pwrsts_mem_on = {
50 [0] = PWRSTS_ON, /* core_nret_bank */ 50 [0] = PWRSTS_ON, /* core_nret_bank */
51 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 51 [1] = PWRSTS_ON, /* core_ocmram */
52 [2] = PWRSTS_ON, /* core_other_bank */ 52 [2] = PWRSTS_ON, /* core_other_bank */
53 [3] = PWRSTS_ON, /* ducati_l2ram */ 53 [3] = PWRSTS_ON, /* ducati_l2ram */
54 [4] = PWRSTS_ON, /* ducati_unicache */ 54 [4] = PWRSTS_ON, /* ducati_unicache */
@@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
318 .prcm_partition = OMAP4430_PRM_PARTITION, 318 .prcm_partition = OMAP4430_PRM_PARTITION,
319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
320 .pwrsts = PWRSTS_OFF_ON, 320 .pwrsts = PWRSTS_OFF_ON,
321 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
321}; 322};
322 323
323/* 324/*