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authorGuoqing Li <ligq@marvell.com>2013-09-13 02:59:45 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2013-09-20 05:52:32 -0400
commit9a27d5916b1d0338f76a4a8cb6fabc5320664453 (patch)
treeab0e09e7e188f6fdde524ecf03a56290b3f47c20
parent91f8628b7f7fe82af389ca99fffa1f132cb6afbf (diff)
video: mmp: rb swap setting update for mmp display
We could set rb swap in two modules: DMA controler input part and dsi interface output part. DMA input part is based on pix_fmt to set rbswap, dsi output interface part will set rbswap based on platform dsi_rbswap configuration. This patch include below change and enhancement: 1) The input format which support rbswap is based on RGB format, eg. RGB565 indicates the source data in memory is that Red is [15~11], Green is [10~5], Blue is [4:0], Red is MSB, Blue is LSB, but for the display dma input default setting(rbswap = 0), it only support Blue is [15~11], Green is [10~5], Red is [4:0], Red is LSB, Blue is MSB, so for this format(RGB565), display controller need to set rbswap = 1 and it can support the MSB/LSB correctly. BGR/YUV format will not set it in mmp display driver. 2) The dsi output part of rbswap is depend on dsi_rbswap which is defined in specific platfrom. For output dsi interface, it has this feature to do rbswap again if it needs specifc byte sequence of RGB byte for DSI panel. eg. If display content is set RGB565 in memory and DMA input part set rbswap in driver to support Red as MSB , Blue LSB, but dsi panel only support Red as LSB, Blue as MSB, then it can use this feature. If there is no this requirement of panel, this dsi output part is not needed. Signed-off-by: Guoqing Li <ligq@marvell.com> Signed-off-by: Jett.Zhou <jtzhou@marvell.com> Signed-off-by: Zhou Zhu <zzhu3@marvell.com> Reviewed-by: Daniel Drake <dsd@laptop.org> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
-rw-r--r--drivers/video/mmp/hw/mmp_ctrl.c19
-rw-r--r--drivers/video/mmp/hw/mmp_ctrl.h5
-rw-r--r--include/video/mmp_disp.h1
3 files changed, 17 insertions, 8 deletions
diff --git a/drivers/video/mmp/hw/mmp_ctrl.c b/drivers/video/mmp/hw/mmp_ctrl.c
index 75dca19bf214..a40d95a54eec 100644
--- a/drivers/video/mmp/hw/mmp_ctrl.c
+++ b/drivers/video/mmp/hw/mmp_ctrl.c
@@ -60,8 +60,7 @@ static irqreturn_t ctrl_handle_irq(int irq, void *dev_id)
60 60
61static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt) 61static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
62{ 62{
63 u32 link_config = path_to_path_plat(overlay->path)->link_config; 63 u32 rbswap = 0, uvswap = 0, yuvswap = 0,
64 u32 rbswap, uvswap = 0, yuvswap = 0,
65 csc_en = 0, val = 0, 64 csc_en = 0, val = 0,
66 vid = overlay_is_vid(overlay); 65 vid = overlay_is_vid(overlay);
67 66
@@ -71,27 +70,23 @@ static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
71 case PIXFMT_RGB888PACK: 70 case PIXFMT_RGB888PACK:
72 case PIXFMT_RGB888UNPACK: 71 case PIXFMT_RGB888UNPACK:
73 case PIXFMT_RGBA888: 72 case PIXFMT_RGBA888:
74 rbswap = !(link_config & 0x1); 73 rbswap = 1;
75 break; 74 break;
76 case PIXFMT_VYUY: 75 case PIXFMT_VYUY:
77 case PIXFMT_YVU422P: 76 case PIXFMT_YVU422P:
78 case PIXFMT_YVU420P: 77 case PIXFMT_YVU420P:
79 rbswap = link_config & 0x1;
80 uvswap = 1; 78 uvswap = 1;
81 break; 79 break;
82 case PIXFMT_YUYV: 80 case PIXFMT_YUYV:
83 rbswap = link_config & 0x1;
84 yuvswap = 1; 81 yuvswap = 1;
85 break; 82 break;
86 default: 83 default:
87 rbswap = link_config & 0x1;
88 break; 84 break;
89 } 85 }
90 86
91 switch (pix_fmt) { 87 switch (pix_fmt) {
92 case PIXFMT_RGB565: 88 case PIXFMT_RGB565:
93 case PIXFMT_BGR565: 89 case PIXFMT_BGR565:
94 val = 0;
95 break; 90 break;
96 case PIXFMT_RGB1555: 91 case PIXFMT_RGB1555:
97 case PIXFMT_BGR1555: 92 case PIXFMT_BGR1555:
@@ -248,7 +243,8 @@ static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
248{ 243{
249 struct lcd_regs *regs = path_regs(path); 244 struct lcd_regs *regs = path_regs(path);
250 u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div, 245 u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
251 link_config = path_to_path_plat(path)->link_config; 246 link_config = path_to_path_plat(path)->link_config,
247 dsi_rbswap = path_to_path_plat(path)->link_config;
252 248
253 /* FIXME: assert videomode supported */ 249 /* FIXME: assert videomode supported */
254 memcpy(&path->mode, mode, sizeof(struct mmp_mode)); 250 memcpy(&path->mode, mode, sizeof(struct mmp_mode));
@@ -263,6 +259,12 @@ static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
263 tmp |= CFG_DUMB_ENA(1); 259 tmp |= CFG_DUMB_ENA(1);
264 writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id)); 260 writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
265 261
262 /* interface rb_swap setting */
263 tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
264 (~(CFG_INTFRBSWAP_MASK));
265 tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;
266 writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
267
266 writel_relaxed((mode->yres << 16) | mode->xres, &regs->screen_active); 268 writel_relaxed((mode->yres << 16) | mode->xres, &regs->screen_active);
267 writel_relaxed((mode->left_margin << 16) | mode->right_margin, 269 writel_relaxed((mode->left_margin << 16) | mode->right_margin,
268 &regs->screen_h_porch); 270 &regs->screen_h_porch);
@@ -419,6 +421,7 @@ static int path_init(struct mmphw_path_plat *path_plat,
419 path_plat->path = path; 421 path_plat->path = path;
420 path_plat->path_config = config->path_config; 422 path_plat->path_config = config->path_config;
421 path_plat->link_config = config->link_config; 423 path_plat->link_config = config->link_config;
424 path_plat->dsi_rbswap = config->dsi_rbswap;
422 path_set_default(path); 425 path_set_default(path);
423 426
424 kfree(path_info); 427 kfree(path_info);
diff --git a/drivers/video/mmp/hw/mmp_ctrl.h b/drivers/video/mmp/hw/mmp_ctrl.h
index edd2002b0e99..53301cfdb1ae 100644
--- a/drivers/video/mmp/hw/mmp_ctrl.h
+++ b/drivers/video/mmp/hw/mmp_ctrl.h
@@ -163,6 +163,8 @@ struct lcd_regs {
163 163
164#define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\ 164#define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
165 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV)) 165 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
166#define intf_rbswap_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \
167 PN2_IOPAD_CONTROL) : LCD_TOP_CTRL)
166 168
167/* dither configure */ 169/* dither configure */
168#ifdef CONFIG_CPU_PXA988 170#ifdef CONFIG_CPU_PXA988
@@ -615,6 +617,8 @@ struct lcd_regs {
615#define LCD_SPU_DUMB_CTRL 0x01B8 617#define LCD_SPU_DUMB_CTRL 0x01B8
616#define CFG_DUMBMODE(mode) ((mode)<<28) 618#define CFG_DUMBMODE(mode) ((mode)<<28)
617#define CFG_DUMBMODE_MASK 0xF0000000 619#define CFG_DUMBMODE_MASK 0xF0000000
620#define CFG_INTFRBSWAP(mode) ((mode)<<24)
621#define CFG_INTFRBSWAP_MASK 0x0F000000
618#define CFG_LCDGPIO_O(data) ((data)<<20) 622#define CFG_LCDGPIO_O(data) ((data)<<20)
619#define CFG_LCDGPIO_O_MASK 0x0FF00000 623#define CFG_LCDGPIO_O_MASK 0x0FF00000
620#define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12) 624#define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12)
@@ -1427,6 +1431,7 @@ struct mmphw_path_plat {
1427 struct mmp_path *path; 1431 struct mmp_path *path;
1428 u32 path_config; 1432 u32 path_config;
1429 u32 link_config; 1433 u32 link_config;
1434 u32 dsi_rbswap;
1430}; 1435};
1431 1436
1432/* mmp ctrl describes mmp controller related info */ 1437/* mmp ctrl describes mmp controller related info */
diff --git a/include/video/mmp_disp.h b/include/video/mmp_disp.h
index b9dd1fbb0082..32094c052deb 100644
--- a/include/video/mmp_disp.h
+++ b/include/video/mmp_disp.h
@@ -334,6 +334,7 @@ struct mmp_mach_path_config {
334 int output_type; 334 int output_type;
335 u32 path_config; 335 u32 path_config;
336 u32 link_config; 336 u32 link_config;
337 u32 dsi_rbswap;
337}; 338};
338 339
339struct mmp_mach_plat_info { 340struct mmp_mach_plat_info {