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authorFabio Estevam <fabio.estevam@freescale.com>2014-09-05 08:46:10 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-09-15 22:26:04 -0400
commit9a060c1a3bb8f5f3940ddb82cb7aa76a843b96cc (patch)
tree3f1314f8c15be40ef1b592fd463e2a26f6c635a0
parent433fb101132047383b550c58585b5a38797c90d1 (diff)
ARM: dts: imx6qdl-sabresd: Configure the pins locally
Passing '0x80000000' to the pin configuration means that kernel will skip the IOMUXC_SW_PAD_CTL configuration and will use whathever values come from the bootloader. Instead of relying on the bootloader setup, let's configure it in the kernel to have predictable settings. '0x1b0b0' is the default POR value for all these pins and has also been verified that the pins are using this value by manually inspecting the IOMUXC_SW_PAD_CTL registers, so no functional change has been made. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi26
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 07fb3020e1bf..baf2f00d519a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -327,15 +327,15 @@
327 imx6qdl-sabresd { 327 imx6qdl-sabresd {
328 pinctrl_hog: hoggrp { 328 pinctrl_hog: hoggrp {
329 fsl,pins = < 329 fsl,pins = <
330 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 330 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
331 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 331 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
332 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 332 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
333 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 333 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
334 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 334 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
335 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 335 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
336 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 336 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
337 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 337 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
338 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 338 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
339 >; 339 >;
340 }; 340 };
341 341
@@ -380,9 +380,9 @@
380 380
381 pinctrl_gpio_keys: gpio_keysgrp { 381 pinctrl_gpio_keys: gpio_keysgrp {
382 fsl,pins = < 382 fsl,pins = <
383 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 383 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
384 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 384 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
385 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 385 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
386 >; 386 >;
387 }; 387 };
388 388
@@ -409,7 +409,7 @@
409 409
410 pinctrl_pcie: pciegrp { 410 pinctrl_pcie: pciegrp {
411 fsl,pins = < 411 fsl,pins = <
412 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 412 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
413 >; 413 >;
414 }; 414 };
415 415
@@ -487,7 +487,7 @@
487 gpio_leds { 487 gpio_leds {
488 pinctrl_gpio_leds: gpioledsgrp { 488 pinctrl_gpio_leds: gpioledsgrp {
489 fsl,pins = < 489 fsl,pins = <
490 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 490 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
491 >; 491 >;
492 }; 492 };
493 }; 493 };