drm/i915: Move intel_init_pipe_control out of engine->init_hw

With this all the ->init_hw hooks really only set up hw state needed
to start the ring, all the software state setup and memory/buffer
allocations happen beforehand.

v2: We need to call intel_init_pipe_control after the ring init since
otherwise engine->dev is NULL and it falls over. Currently that's
now after the hw ring is enabled but a) we'll be fine as long as no
one submits a batch b) this will change soon.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 18 insertions, 12 deletions

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5e9bb531aeef..542382f2b1d5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1161,10 +1161,6 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring)
          */
         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 
-        ret = intel_init_pipe_control(ring);
-        if (ret)
-                return ret;
-
         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
         return init_workarounds_ring(ring);
@@ -1406,6 +1402,7 @@ static int logical_render_ring_init(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
+        int ret;
 
         ring->name = "render ring";
         ring->id = RCS;
@@ -1428,7 +1425,12 @@ static int logical_render_ring_init(struct drm_device *dev)
         ring->irq_put = gen8_logical_ring_put_irq;
         ring->emit_bb_start = gen8_emit_bb_start;
 
-        return logical_ring_init(dev, ring);
+        ring->dev = dev;
+        ret = logical_ring_init(dev, ring);
+        if (ret)
+                return ret;
+
+        return intel_init_pipe_control(ring);
 }
 
 static int logical_bsd_ring_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2a87b2261350..f0ffcf7c7eb3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -865,12 +865,6 @@ static int init_render_ring(struct intel_engine_cs *ring)
                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 
-        if (INTEL_INFO(dev)->gen >= 5) {
-                ret = intel_init_pipe_control(ring);
-                if (ret)
-                        return ret;
-        }
-
         if (IS_GEN6(dev)) {
                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
                  * "If this bit is set, STCunit will have LRA as replacement
@@ -2459,7 +2453,17 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
         }
 
-        return intel_init_ring_buffer(dev, ring);
+        ret = intel_init_ring_buffer(dev, ring);
+        if (ret)
+                return ret;
+
+        if (INTEL_INFO(dev)->gen >= 5) {
+                ret = intel_init_pipe_control(ring);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
 }
 
 int intel_init_bsd_ring_buffer(struct drm_device *dev)