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authorNithin Sujir <nsujir@broadcom.com>2013-08-30 20:01:36 -0400
committerDavid S. Miller <davem@davemloft.net>2013-09-03 22:23:40 -0400
commit989038e217e94161862a959e82f9a1ecf8dda152 (patch)
treea672cd09f7b77826a8166e77638b5e29230a1152
parent535a69e94fbf77397e0ec354a58e8e51d41e944e (diff)
tg3: Don't turn off led on 5719 serdes port 0
Turning off led on port 0 of the 5719 serdes causes all other ports to lose power and stop functioning. Add tg3_phy_led_bug() function to check for this condition. We use a switch() in tg3_phy_led_bug() for consistency with the tg3_phy_power_bug() function. Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/broadcom/tg3.c18
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 0da2214ef1b9..9d289d33f66d 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -3030,6 +3030,19 @@ static bool tg3_phy_power_bug(struct tg3 *tp)
3030 return false; 3030 return false;
3031} 3031}
3032 3032
3033static bool tg3_phy_led_bug(struct tg3 *tp)
3034{
3035 switch (tg3_asic_rev(tp)) {
3036 case ASIC_REV_5719:
3037 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3038 !tp->pci_fn)
3039 return true;
3040 return false;
3041 }
3042
3043 return false;
3044}
3045
3033static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) 3046static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3034{ 3047{
3035 u32 val; 3048 u32 val;
@@ -3077,8 +3090,9 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3077 } 3090 }
3078 return; 3091 return;
3079 } else if (do_low_power) { 3092 } else if (do_low_power) {
3080 tg3_writephy(tp, MII_TG3_EXT_CTRL, 3093 if (!tg3_phy_led_bug(tp))
3081 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 3094 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3095 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3082 3096
3083 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | 3097 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | 3098 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |