ARM: zynq: add gem support

The zynq includes a Cadence GEM IP core. This is compatible with the macb driver.
Add it to the zynq-7000 DT.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Josh Cartwright <josh.cartwright@ni.com>
[soren: rebased to current Linus tree, added zc706 + zed support, moved phy-mode property to board level dtses]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

4 files changed, 33 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index e7f73b2e4550..aebc48d8c397 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -65,6 +65,24 @@
                         interrupts = <0 50 4>;
                 };
 
+                gem0: ethernet@e000b000 {
+                        compatible = "cdns,gem";
+                        reg = <0xe000b000 0x4000>;
+                        status = "disabled";
+                        interrupts = <0 22 4>;
+                        clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
+                        clock-names = "pclk", "hclk", "tx_clk";
+                };
+
+                gem1: ethernet@e000c000 {
+                        compatible = "cdns,gem";
+                        reg = <0xe000c000 0x4000>;
+                        status = "disabled";
+                        interrupts = <0 45 4>;
+                        clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
+                        clock-names = "pclk", "hclk", "tx_clk";
+                };
+
                 slcr: slcr@f8000000 {
                         compatible = "xlnx,zynq-slcr";
                         reg = <0xF8000000 0x1000>;
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 21aea99a067b..34d680a46b7e 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -29,6 +29,11 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 79009e0b74b9..b2835d5fc09a 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -30,6 +30,11 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index d6acf2b1cdf4..2eda06889dfc 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -30,6 +30,11 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
 &uart1 {
         status = "okay";
 };