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authorLinus Torvalds <torvalds@linux-foundation.org>2014-11-04 00:06:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-11-04 00:06:22 -0500
commit980d0d51b1c9617a472b2c0fcbe33d2d15eadc4c (patch)
tree79007bcc72b43a1a2499caa6f57714b0f2699d1c
parentf3ed88a6bce69942b44fa7927a92cd52011881d7 (diff)
parentd90c33818967c5e5371961604ad98b4dea4fa3f4 (diff)
Merge tag 'pinctrl-v3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin-control fixes from Linus Walleij: "This kernel cycle has been calm for both pin control and GPIO so far but here are three pin control patches for you anyway, only really dealing with Baytrail: - Two fixes for the Baytrail driver affecting IRQs and output state in sysfs - Use the linux-gpio mailing list also for pinctrl patches" * tag 'pinctrl-v3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: baytrail: show output gpio state correctly on Intel Baytrail pinctrl: use linux-gpio mailing list pinctrl: baytrail: Clear DIRECT_IRQ bit
-rw-r--r--MAINTAINERS1
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c8
2 files changed, 7 insertions, 2 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index f155c2a1255e..5d6136b8959e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7180,6 +7180,7 @@ F: drivers/crypto/picoxcell*
7180 7180
7181PIN CONTROL SUBSYSTEM 7181PIN CONTROL SUBSYSTEM
7182M: Linus Walleij <linus.walleij@linaro.org> 7182M: Linus Walleij <linus.walleij@linaro.org>
7183L: linux-gpio@vger.kernel.org
7183S: Maintained 7184S: Maintained
7184F: drivers/pinctrl/ 7185F: drivers/pinctrl/
7185F: include/linux/pinctrl/ 7186F: include/linux/pinctrl/
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
index e12e5b07f6d7..9dc38140194b 100644
--- a/drivers/pinctrl/pinctrl-baytrail.c
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -227,10 +227,14 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
227 spin_lock_irqsave(&vg->lock, flags); 227 spin_lock_irqsave(&vg->lock, flags);
228 value = readl(reg); 228 value = readl(reg);
229 229
230 WARN(value & BYT_DIRECT_IRQ_EN,
231 "Bad pad config for io mode, force direct_irq_en bit clearing");
232
230 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 233 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
231 * are used to indicate high and low level triggering 234 * are used to indicate high and low level triggering
232 */ 235 */
233 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 236 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
237 BYT_TRIG_LVL);
234 238
235 switch (type) { 239 switch (type) {
236 case IRQ_TYPE_LEVEL_HIGH: 240 case IRQ_TYPE_LEVEL_HIGH:
@@ -318,7 +322,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
318 "Potential Error: Setting GPIO with direct_irq_en to output"); 322 "Potential Error: Setting GPIO with direct_irq_en to output");
319 323
320 reg_val = readl(reg) | BYT_DIR_MASK; 324 reg_val = readl(reg) | BYT_DIR_MASK;
321 reg_val &= ~BYT_OUTPUT_EN; 325 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
322 326
323 if (value) 327 if (value)
324 writel(reg_val | BYT_LEVEL, reg); 328 writel(reg_val | BYT_LEVEL, reg);