diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2014-06-19 17:34:41 -0400 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-06-24 08:38:07 -0400 |
| commit | 97dcc21bd3dc7f04a48ff37700ae838feb35fca4 (patch) | |
| tree | f96def3ea47d6475a0b83436ac9603d3bbb6eacc | |
| parent | 4ecc832f4ef25dcb684ca986de3612e881748c0e (diff) | |
irqchip: spear_shirq: Kill the clear_reg nonsense
None of the chips has a ACK register. The code brainlessly fiddles
with the enable register, so it might even reenable a disabled
interrupt at least on spear300.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.570396433@linutronix.de
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| -rw-r--r-- | drivers/irqchip/spear-shirq.c | 35 |
1 files changed, 1 insertions, 34 deletions
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c index fc57c35a20b4..2a33129c4f4b 100644 --- a/drivers/irqchip/spear-shirq.c +++ b/drivers/irqchip/spear-shirq.c | |||
| @@ -33,15 +33,11 @@ | |||
| 33 | * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt | 33 | * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt |
| 34 | * status_reg: status register offset | 34 | * status_reg: status register offset |
| 35 | * status_reg_mask: status register valid mask | 35 | * status_reg_mask: status register valid mask |
| 36 | * clear_reg: clear register offset | ||
| 37 | * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt | ||
| 38 | */ | 36 | */ |
| 39 | struct shirq_regs { | 37 | struct shirq_regs { |
| 40 | u32 enb_reg; | 38 | u32 enb_reg; |
| 41 | u32 reset_to_enb; | 39 | u32 reset_to_enb; |
| 42 | u32 status_reg; | 40 | u32 status_reg; |
| 43 | u32 clear_reg; | ||
| 44 | u32 reset_to_clear; | ||
| 45 | }; | 41 | }; |
| 46 | 42 | ||
| 47 | /* | 43 | /* |
| @@ -78,7 +74,6 @@ static struct spear_shirq spear300_shirq_ras1 = { | |||
| 78 | .regs = { | 74 | .regs = { |
| 79 | .enb_reg = SPEAR300_INT_ENB_MASK_REG, | 75 | .enb_reg = SPEAR300_INT_ENB_MASK_REG, |
| 80 | .status_reg = SPEAR300_INT_STS_MASK_REG, | 76 | .status_reg = SPEAR300_INT_STS_MASK_REG, |
| 81 | .clear_reg = -1, | ||
| 82 | }, | 77 | }, |
| 83 | }; | 78 | }; |
| 84 | 79 | ||
| @@ -96,7 +91,6 @@ static struct spear_shirq spear310_shirq_ras1 = { | |||
| 96 | .regs = { | 91 | .regs = { |
| 97 | .enb_reg = -1, | 92 | .enb_reg = -1, |
| 98 | .status_reg = SPEAR310_INT_STS_MASK_REG, | 93 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 99 | .clear_reg = -1, | ||
| 100 | }, | 94 | }, |
| 101 | }; | 95 | }; |
| 102 | 96 | ||
| @@ -107,7 +101,6 @@ static struct spear_shirq spear310_shirq_ras2 = { | |||
| 107 | .regs = { | 101 | .regs = { |
| 108 | .enb_reg = -1, | 102 | .enb_reg = -1, |
| 109 | .status_reg = SPEAR310_INT_STS_MASK_REG, | 103 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 110 | .clear_reg = -1, | ||
| 111 | }, | 104 | }, |
| 112 | }; | 105 | }; |
| 113 | 106 | ||
| @@ -118,7 +111,6 @@ static struct spear_shirq spear310_shirq_ras3 = { | |||
| 118 | .regs = { | 111 | .regs = { |
| 119 | .enb_reg = -1, | 112 | .enb_reg = -1, |
| 120 | .status_reg = SPEAR310_INT_STS_MASK_REG, | 113 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 121 | .clear_reg = -1, | ||
| 122 | }, | 114 | }, |
| 123 | }; | 115 | }; |
| 124 | 116 | ||
| @@ -129,7 +121,6 @@ static struct spear_shirq spear310_shirq_intrcomm_ras = { | |||
| 129 | .regs = { | 121 | .regs = { |
| 130 | .enb_reg = -1, | 122 | .enb_reg = -1, |
| 131 | .status_reg = SPEAR310_INT_STS_MASK_REG, | 123 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 132 | .clear_reg = -1, | ||
| 133 | }, | 124 | }, |
| 134 | }; | 125 | }; |
| 135 | 126 | ||
| @@ -150,13 +141,6 @@ static struct spear_shirq spear320_shirq_ras3 = { | |||
| 150 | .nr_irqs = 7, | 141 | .nr_irqs = 7, |
| 151 | .mask = ((0x1 << 7) - 1) << 0, | 142 | .mask = ((0x1 << 7) - 1) << 0, |
| 152 | .disabled = 1, | 143 | .disabled = 1, |
| 153 | .regs = { | ||
| 154 | .enb_reg = SPEAR320_INT_ENB_MASK_REG, | ||
| 155 | .reset_to_enb = 1, | ||
| 156 | .status_reg = SPEAR320_INT_STS_MASK_REG, | ||
| 157 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | ||
| 158 | .reset_to_clear = 1, | ||
| 159 | }, | ||
| 160 | }; | 144 | }; |
| 161 | 145 | ||
| 162 | static struct spear_shirq spear320_shirq_ras1 = { | 146 | static struct spear_shirq spear320_shirq_ras1 = { |
| @@ -166,8 +150,6 @@ static struct spear_shirq spear320_shirq_ras1 = { | |||
| 166 | .regs = { | 150 | .regs = { |
| 167 | .enb_reg = -1, | 151 | .enb_reg = -1, |
| 168 | .status_reg = SPEAR320_INT_STS_MASK_REG, | 152 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
| 169 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | ||
| 170 | .reset_to_clear = 1, | ||
| 171 | }, | 153 | }, |
| 172 | }; | 154 | }; |
| 173 | 155 | ||
| @@ -178,8 +160,6 @@ static struct spear_shirq spear320_shirq_ras2 = { | |||
| 178 | .regs = { | 160 | .regs = { |
| 179 | .enb_reg = -1, | 161 | .enb_reg = -1, |
| 180 | .status_reg = SPEAR320_INT_STS_MASK_REG, | 162 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
| 181 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | ||
| 182 | .reset_to_clear = 1, | ||
| 183 | }, | 163 | }, |
| 184 | }; | 164 | }; |
| 185 | 165 | ||
| @@ -190,8 +170,6 @@ static struct spear_shirq spear320_shirq_intrcomm_ras = { | |||
| 190 | .regs = { | 170 | .regs = { |
| 191 | .enb_reg = -1, | 171 | .enb_reg = -1, |
| 192 | .status_reg = SPEAR320_INT_STS_MASK_REG, | 172 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
| 193 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | ||
| 194 | .reset_to_clear = 1, | ||
| 195 | }, | 173 | }, |
| 196 | }; | 174 | }; |
| 197 | 175 | ||
| @@ -246,7 +224,7 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc) | |||
| 246 | struct spear_shirq *shirq = irq_get_handler_data(irq); | 224 | struct spear_shirq *shirq = irq_get_handler_data(irq); |
| 247 | struct irq_data *idata = irq_desc_get_irq_data(desc); | 225 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
| 248 | struct irq_chip *chip = irq_data_get_irq_chip(idata); | 226 | struct irq_chip *chip = irq_data_get_irq_chip(idata); |
| 249 | u32 i, j, val, mask, tmp; | 227 | u32 i, j, val, mask; |
| 250 | 228 | ||
| 251 | chip->irq_ack(idata); | 229 | chip->irq_ack(idata); |
| 252 | 230 | ||
| @@ -261,17 +239,6 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc) | |||
| 261 | continue; | 239 | continue; |
| 262 | 240 | ||
| 263 | generic_handle_irq(shirq->virq_base + i); | 241 | generic_handle_irq(shirq->virq_base + i); |
| 264 | |||
| 265 | /* clear interrupt */ | ||
| 266 | if (shirq->regs.clear_reg == -1) | ||
| 267 | continue; | ||
| 268 | |||
| 269 | tmp = readl(shirq->base + shirq->regs.clear_reg); | ||
| 270 | if (shirq->regs.reset_to_clear) | ||
| 271 | tmp &= ~(j << shirq->offset); | ||
| 272 | else | ||
| 273 | tmp |= (j << shirq->offset); | ||
| 274 | writel(tmp, shirq->base + shirq->regs.clear_reg); | ||
| 275 | } | 242 | } |
| 276 | } | 243 | } |
| 277 | chip->irq_unmask(idata); | 244 | chip->irq_unmask(idata); |
