diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-03-31 23:10:45 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-05-15 20:48:33 -0400 |
commit | 96c50082904c7cefa3b01356f62268ee6d9e9f38 (patch) | |
tree | a735093f5a7a9f4489bae195bd0809e714ba70a2 | |
parent | 4976986bd4f51368890f57b964176ec532972543 (diff) |
drm/nouveau: move set_tile_region to nouveau_exec_engine
In the very least VPE (PMPEG and friends) also has this style of tile
region regs, lets make them just work if/when they get added.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_state.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv10_graph.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv20_graph.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv40_graph.c | 3 |
6 files changed, 12 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index fb33d4f096c5..413e2ba5e4d8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -302,6 +302,7 @@ struct nouveau_exec_engine { | |||
302 | void (*context_del)(struct nouveau_channel *, int engine); | 302 | void (*context_del)(struct nouveau_channel *, int engine); |
303 | int (*object_new)(struct nouveau_channel *, int engine, | 303 | int (*object_new)(struct nouveau_channel *, int engine, |
304 | u32 handle, u16 class); | 304 | u32 handle, u16 class); |
305 | void (*set_tile_region)(struct drm_device *dev, int i); | ||
305 | void (*tlb_flush)(struct drm_device *, int engine); | 306 | void (*tlb_flush)(struct drm_device *, int engine); |
306 | }; | 307 | }; |
307 | 308 | ||
@@ -393,7 +394,6 @@ struct nouveau_pgraph_engine { | |||
393 | int (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class); | 394 | int (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class); |
394 | void (*tlb_flush)(struct drm_device *dev); | 395 | void (*tlb_flush)(struct drm_device *dev); |
395 | 396 | ||
396 | void (*set_tile_region)(struct drm_device *dev, int i); | ||
397 | }; | 397 | }; |
398 | 398 | ||
399 | struct nouveau_display_engine { | 399 | struct nouveau_display_engine { |
@@ -1151,18 +1151,15 @@ extern struct nouveau_bitfield nv04_graph_nsource[]; | |||
1151 | /* nv10_graph.c */ | 1151 | /* nv10_graph.c */ |
1152 | extern int nv10_graph_create(struct drm_device *); | 1152 | extern int nv10_graph_create(struct drm_device *); |
1153 | extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); | 1153 | extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); |
1154 | extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); | ||
1155 | extern struct nouveau_bitfield nv10_graph_intr[]; | 1154 | extern struct nouveau_bitfield nv10_graph_intr[]; |
1156 | extern struct nouveau_bitfield nv10_graph_nstatus[]; | 1155 | extern struct nouveau_bitfield nv10_graph_nstatus[]; |
1157 | 1156 | ||
1158 | /* nv20_graph.c */ | 1157 | /* nv20_graph.c */ |
1159 | extern int nv20_graph_create(struct drm_device *); | 1158 | extern int nv20_graph_create(struct drm_device *); |
1160 | extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); | ||
1161 | 1159 | ||
1162 | /* nv40_graph.c */ | 1160 | /* nv40_graph.c */ |
1163 | extern int nv40_graph_create(struct drm_device *); | 1161 | extern int nv40_graph_create(struct drm_device *); |
1164 | extern void nv40_grctx_init(struct nouveau_grctx *); | 1162 | extern void nv40_grctx_init(struct nouveau_grctx *); |
1165 | extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); | ||
1166 | 1163 | ||
1167 | /* nv50_graph.c */ | 1164 | /* nv50_graph.c */ |
1168 | extern int nv50_graph_create(struct drm_device *); | 1165 | extern int nv50_graph_create(struct drm_device *); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index cf1731bbb032..9c7bc3f396c4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -51,8 +51,7 @@ nv10_mem_update_tile_region(struct drm_device *dev, | |||
51 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 51 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
52 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; | 52 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
53 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; | 53 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; |
54 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | 54 | int i = tile - dev_priv->tile.reg, j; |
55 | int i = tile - dev_priv->tile.reg; | ||
56 | unsigned long save; | 55 | unsigned long save; |
57 | 56 | ||
58 | nouveau_fence_unref(&tile->fence); | 57 | nouveau_fence_unref(&tile->fence); |
@@ -70,7 +69,10 @@ nv10_mem_update_tile_region(struct drm_device *dev, | |||
70 | nouveau_wait_for_idle(dev); | 69 | nouveau_wait_for_idle(dev); |
71 | 70 | ||
72 | pfb->set_tile_region(dev, i); | 71 | pfb->set_tile_region(dev, i); |
73 | pgraph->set_tile_region(dev, i); | 72 | for (j = 0; j < NVOBJ_ENGINE_NR; j++) { |
73 | if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region) | ||
74 | dev_priv->eng[j]->set_tile_region(dev, i); | ||
75 | } | ||
74 | 76 | ||
75 | pfifo->cache_pull(dev, true); | 77 | pfifo->cache_pull(dev, true); |
76 | pfifo->reassign(dev, true); | 78 | pfifo->reassign(dev, true); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 2a127edc2bcf..052a26777992 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c | |||
@@ -121,7 +121,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
121 | engine->graph.takedown = nouveau_stub_takedown; | 121 | engine->graph.takedown = nouveau_stub_takedown; |
122 | engine->graph.channel = nvc0_graph_channel; | 122 | engine->graph.channel = nvc0_graph_channel; |
123 | engine->graph.fifo_access = nvc0_graph_fifo_access; | 123 | engine->graph.fifo_access = nvc0_graph_fifo_access; |
124 | engine->graph.set_tile_region = nv10_graph_set_tile_region; | ||
125 | engine->fifo.channels = 32; | 124 | engine->fifo.channels = 32; |
126 | engine->fifo.init = nv10_fifo_init; | 125 | engine->fifo.init = nv10_fifo_init; |
127 | engine->fifo.takedown = nv04_fifo_fini; | 126 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -174,7 +173,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
174 | engine->graph.takedown = nouveau_stub_takedown; | 173 | engine->graph.takedown = nouveau_stub_takedown; |
175 | engine->graph.channel = nvc0_graph_channel; | 174 | engine->graph.channel = nvc0_graph_channel; |
176 | engine->graph.fifo_access = nvc0_graph_fifo_access; | 175 | engine->graph.fifo_access = nvc0_graph_fifo_access; |
177 | engine->graph.set_tile_region = nv20_graph_set_tile_region; | ||
178 | engine->fifo.channels = 32; | 176 | engine->fifo.channels = 32; |
179 | engine->fifo.init = nv10_fifo_init; | 177 | engine->fifo.init = nv10_fifo_init; |
180 | engine->fifo.takedown = nv04_fifo_fini; | 178 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -227,7 +225,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
227 | engine->graph.takedown = nouveau_stub_takedown; | 225 | engine->graph.takedown = nouveau_stub_takedown; |
228 | engine->graph.channel = nvc0_graph_channel; | 226 | engine->graph.channel = nvc0_graph_channel; |
229 | engine->graph.fifo_access = nvc0_graph_fifo_access; | 227 | engine->graph.fifo_access = nvc0_graph_fifo_access; |
230 | engine->graph.set_tile_region = nv20_graph_set_tile_region; | ||
231 | engine->fifo.channels = 32; | 228 | engine->fifo.channels = 32; |
232 | engine->fifo.init = nv10_fifo_init; | 229 | engine->fifo.init = nv10_fifo_init; |
233 | engine->fifo.takedown = nv04_fifo_fini; | 230 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -283,7 +280,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
283 | engine->graph.takedown = nouveau_stub_takedown; | 280 | engine->graph.takedown = nouveau_stub_takedown; |
284 | engine->graph.fifo_access = nvc0_graph_fifo_access; | 281 | engine->graph.fifo_access = nvc0_graph_fifo_access; |
285 | engine->graph.channel = nvc0_graph_channel; | 282 | engine->graph.channel = nvc0_graph_channel; |
286 | engine->graph.set_tile_region = nv40_graph_set_tile_region; | ||
287 | engine->fifo.channels = 32; | 283 | engine->fifo.channels = 32; |
288 | engine->fifo.init = nv40_fifo_init; | 284 | engine->fifo.init = nv40_fifo_init; |
289 | engine->fifo.takedown = nv04_fifo_fini; | 285 | engine->fifo.takedown = nv04_fifo_fini; |
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c index afc456bb2beb..0930c6cb88e0 100644 --- a/drivers/gpu/drm/nouveau/nv10_graph.c +++ b/drivers/gpu/drm/nouveau/nv10_graph.c | |||
@@ -893,7 +893,7 @@ nv10_graph_context_del(struct nouveau_channel *chan, int engine) | |||
893 | kfree(pgraph_ctx); | 893 | kfree(pgraph_ctx); |
894 | } | 894 | } |
895 | 895 | ||
896 | void | 896 | static void |
897 | nv10_graph_set_tile_region(struct drm_device *dev, int i) | 897 | nv10_graph_set_tile_region(struct drm_device *dev, int i) |
898 | { | 898 | { |
899 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 899 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
@@ -1143,6 +1143,7 @@ nv10_graph_create(struct drm_device *dev) | |||
1143 | pgraph->base.context_new = nv10_graph_context_new; | 1143 | pgraph->base.context_new = nv10_graph_context_new; |
1144 | pgraph->base.context_del = nv10_graph_context_del; | 1144 | pgraph->base.context_del = nv10_graph_context_del; |
1145 | pgraph->base.object_new = nv04_graph_object_new; | 1145 | pgraph->base.object_new = nv04_graph_object_new; |
1146 | pgraph->base.set_tile_region = nv10_graph_set_tile_region; | ||
1146 | 1147 | ||
1147 | NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base); | 1148 | NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base); |
1148 | nouveau_irq_register(dev, 12, nv10_graph_isr); | 1149 | nouveau_irq_register(dev, 12, nv10_graph_isr); |
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c index ce83f02b06dd..b47e9e226e4d 100644 --- a/drivers/gpu/drm/nouveau/nv20_graph.c +++ b/drivers/gpu/drm/nouveau/nv20_graph.c | |||
@@ -470,7 +470,7 @@ nv20_graph_context_del(struct nouveau_channel *chan, int engine) | |||
470 | chan->engctx[engine] = NULL; | 470 | chan->engctx[engine] = NULL; |
471 | } | 471 | } |
472 | 472 | ||
473 | void | 473 | static void |
474 | nv20_graph_set_tile_region(struct drm_device *dev, int i) | 474 | nv20_graph_set_tile_region(struct drm_device *dev, int i) |
475 | { | 475 | { |
476 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 476 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
@@ -730,6 +730,7 @@ nv20_graph_create(struct drm_device *dev) | |||
730 | pgraph->base.context_new = nv20_graph_context_new; | 730 | pgraph->base.context_new = nv20_graph_context_new; |
731 | pgraph->base.context_del = nv20_graph_context_del; | 731 | pgraph->base.context_del = nv20_graph_context_del; |
732 | pgraph->base.object_new = nv04_graph_object_new; | 732 | pgraph->base.object_new = nv04_graph_object_new; |
733 | pgraph->base.set_tile_region = nv20_graph_set_tile_region; | ||
733 | 734 | ||
734 | pgraph->grctx_user = 0x0028; | 735 | pgraph->grctx_user = 0x0028; |
735 | if (dev_priv->card_type == NV_20) { | 736 | if (dev_priv->card_type == NV_20) { |
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c index f0c6a64275aa..638c8878e529 100644 --- a/drivers/gpu/drm/nouveau/nv40_graph.c +++ b/drivers/gpu/drm/nouveau/nv40_graph.c | |||
@@ -207,7 +207,7 @@ nv40_graph_object_new(struct nouveau_channel *chan, int engine, | |||
207 | return ret; | 207 | return ret; |
208 | } | 208 | } |
209 | 209 | ||
210 | void | 210 | static void |
211 | nv40_graph_set_tile_region(struct drm_device *dev, int i) | 211 | nv40_graph_set_tile_region(struct drm_device *dev, int i) |
212 | { | 212 | { |
213 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 213 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
@@ -525,6 +525,7 @@ nv40_graph_create(struct drm_device *dev) | |||
525 | pgraph->base.context_new = nv40_graph_context_new; | 525 | pgraph->base.context_new = nv40_graph_context_new; |
526 | pgraph->base.context_del = nv40_graph_context_del; | 526 | pgraph->base.context_del = nv40_graph_context_del; |
527 | pgraph->base.object_new = nv40_graph_object_new; | 527 | pgraph->base.object_new = nv40_graph_object_new; |
528 | pgraph->base.set_tile_region = nv40_graph_set_tile_region; | ||
528 | 529 | ||
529 | NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base); | 530 | NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base); |
530 | nouveau_irq_register(dev, 12, nv40_graph_isr); | 531 | nouveau_irq_register(dev, 12, nv40_graph_isr); |