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authorYuval Mintz <yuvalmin@broadcom.com>2012-09-30 23:46:19 -0400
committerDavid S. Miller <davem@davemloft.net>2012-10-01 16:43:17 -0400
commit96bed4b954fd5ef69e32f3c1d2c7c6bdda181316 (patch)
tree3c98025e66edbfd135d2e08c55e128ed660ab0c3
parent2f6a02604e962295569749913081365ec9ec1372 (diff)
bnx2x,cnic: use FW 7.8.2
This patch moves the bnx2x and cnic drivers into using FW 7.8.2 which was recently submitted into the linux-firmware tree. A short summary of minor bugs fixed by this FW: 1. In switch dependent mode, fix several issues regarding inner vlan vs. DCB priorities. 2. iSCSI - not all packets were completed on a forward channel. 3. DCB - fixed for 4-port devices. 4. Fixed false parity reported in CAM memories when operating near -5% on the 1.0V core supply. 5. ETS default settings are set to fairness between traffic classes (rather than strict priority), and uses the same chip receive buffer configuration for both PFC and pause. For a complete list of fixes made by this FW, see commit 236367db in the linux-firmware git repository. Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Ariel Elior <ariele@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c12
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c12
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c31
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h3
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h58
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h2
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c504
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c2
-rw-r--r--drivers/net/ethernet/broadcom/cnic.c12
-rw-r--r--drivers/net/ethernet/broadcom/cnic_defs.h2
-rw-r--r--drivers/net/ethernet/broadcom/cnic_if.h4
11 files changed, 79 insertions, 563 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index f67e700fe59d..30f04a389227 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -3026,8 +3026,9 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
3026 first_bd = tx_start_bd; 3026 first_bd = tx_start_bd;
3027 3027
3028 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 3028 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3029 SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_ETH_ADDR_TYPE, 3029 SET_FLAG(tx_start_bd->general_data,
3030 mac_type); 3030 ETH_TX_START_BD_PARSE_NBDS,
3031 0);
3031 3032
3032 /* header nbd */ 3033 /* header nbd */
3033 SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1); 3034 SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1);
@@ -3077,13 +3078,20 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
3077 &pbd_e2->dst_mac_addr_lo, 3078 &pbd_e2->dst_mac_addr_lo,
3078 eth->h_dest); 3079 eth->h_dest);
3079 } 3080 }
3081
3082 SET_FLAG(pbd_e2_parsing_data,
3083 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
3080 } else { 3084 } else {
3085 u16 global_data = 0;
3081 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 3086 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
3082 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 3087 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
3083 /* Set PBD in checksum offload case */ 3088 /* Set PBD in checksum offload case */
3084 if (xmit_type & XMIT_CSUM) 3089 if (xmit_type & XMIT_CSUM)
3085 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type); 3090 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
3086 3091
3092 SET_FLAG(global_data,
3093 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
3094 pbd_e1x->global_data |= cpu_to_le16(global_data);
3087 } 3095 }
3088 3096
3089 /* Setup the data pointer of the first BD of the packet */ 3097 /* Setup the data pointer of the first BD of the packet */
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
index 8a73374e52a7..2245c3895409 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
@@ -91,25 +91,21 @@ static void bnx2x_pfc_set(struct bnx2x *bp)
91 /* 91 /*
92 * Rx COS configuration 92 * Rx COS configuration
93 * Changing PFC RX configuration . 93 * Changing PFC RX configuration .
94 * In RX COS0 will always be configured to lossy and COS1 to lossless 94 * In RX COS0 will always be configured to lossless and COS1 to lossy
95 */ 95 */
96 for (i = 0 ; i < MAX_PFC_PRIORITIES ; i++) { 96 for (i = 0 ; i < MAX_PFC_PRIORITIES ; i++) {
97 pri_bit = 1 << i; 97 pri_bit = 1 << i;
98 98
99 if (pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp)) 99 if (!(pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp)))
100 val |= 1 << (i * 4); 100 val |= 1 << (i * 4);
101 } 101 }
102 102
103 pfc_params.pkt_priority_to_cos = val; 103 pfc_params.pkt_priority_to_cos = val;
104 104
105 /* RX COS0 */ 105 /* RX COS0 */
106 pfc_params.llfc_low_priority_classes = 0; 106 pfc_params.llfc_low_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp);
107 /* RX COS1 */ 107 /* RX COS1 */
108 pfc_params.llfc_high_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp); 108 pfc_params.llfc_high_priority_classes = 0;
109
110 /* BRB configuration */
111 pfc_params.cos0_pauseable = false;
112 pfc_params.cos1_pauseable = true;
113 109
114 bnx2x_acquire_phy_lock(bp); 110 bnx2x_acquire_phy_lock(bp);
115 bp->link_params.feature_config_flags |= FEATURE_CONFIG_PFC_ENABLED; 111 bp->link_params.feature_config_flags |= FEATURE_CONFIG_PFC_ENABLED;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index a19c9e088278..c65295dded39 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -2040,8 +2040,6 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2040 u16 pkt_prod, bd_prod; 2040 u16 pkt_prod, bd_prod;
2041 struct sw_tx_bd *tx_buf; 2041 struct sw_tx_bd *tx_buf;
2042 struct eth_tx_start_bd *tx_start_bd; 2042 struct eth_tx_start_bd *tx_start_bd;
2043 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
2044 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
2045 dma_addr_t mapping; 2043 dma_addr_t mapping;
2046 union eth_rx_cqe *cqe; 2044 union eth_rx_cqe *cqe;
2047 u8 cqe_fp_flags, cqe_fp_type; 2045 u8 cqe_fp_flags, cqe_fp_type;
@@ -2133,21 +2131,32 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2133 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2131 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2134 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2132 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2135 SET_FLAG(tx_start_bd->general_data, 2133 SET_FLAG(tx_start_bd->general_data,
2136 ETH_TX_START_BD_ETH_ADDR_TYPE,
2137 UNICAST_ADDRESS);
2138 SET_FLAG(tx_start_bd->general_data,
2139 ETH_TX_START_BD_HDR_NBDS, 2134 ETH_TX_START_BD_HDR_NBDS,
2140 1); 2135 1);
2136 SET_FLAG(tx_start_bd->general_data,
2137 ETH_TX_START_BD_PARSE_NBDS,
2138 0);
2141 2139
2142 /* turn on parsing and get a BD */ 2140 /* turn on parsing and get a BD */
2143 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2141 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2144 2142
2145 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2143 if (CHIP_IS_E1x(bp)) {
2146 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2144 u16 global_data = 0;
2147 2145 struct eth_tx_parse_bd_e1x *pbd_e1x =
2148 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2146 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2149 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2147 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2150 2148 SET_FLAG(global_data,
2149 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2150 pbd_e1x->global_data = cpu_to_le16(global_data);
2151 } else {
2152 u32 parsing_data = 0;
2153 struct eth_tx_parse_bd_e2 *pbd_e2 =
2154 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2155 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2156 SET_FLAG(parsing_data,
2157 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2158 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2159 }
2151 wmb(); 2160 wmb();
2152 2161
2153 txdata->tx_db.data.prod += 2; 2162 txdata->tx_db.data.prod += 2;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
index bbc66ced9c25..620fe939ecfd 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
@@ -88,9 +88,6 @@
88#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) 88#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
89#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 89#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
90 (IRO[101].base + ((assertListEntry) * IRO[101].m1)) 90 (IRO[101].base + ((assertListEntry) * IRO[101].m1))
91#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET (IRO[107].base)
92#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
93 (IRO[108].base)
94#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ 91#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
95 (IRO[201].base + ((pfId) * IRO[201].m1)) 92 (IRO[201].base + ((pfId) * IRO[201].m1))
96#define TSTORM_FUNC_EN_OFFSET(funcId) \ 93#define TSTORM_FUNC_EN_OFFSET(funcId) \
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
index c795cfc5a545..18704929e642 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
@@ -2789,8 +2789,8 @@ struct afex_stats {
2789}; 2789};
2790 2790
2791#define BCM_5710_FW_MAJOR_VERSION 7 2791#define BCM_5710_FW_MAJOR_VERSION 7
2792#define BCM_5710_FW_MINOR_VERSION 2 2792#define BCM_5710_FW_MINOR_VERSION 8
2793#define BCM_5710_FW_REVISION_VERSION 51 2793#define BCM_5710_FW_REVISION_VERSION 2
2794#define BCM_5710_FW_ENGINEERING_VERSION 0 2794#define BCM_5710_FW_ENGINEERING_VERSION 0
2795#define BCM_5710_FW_COMPILE_FLAGS 1 2795#define BCM_5710_FW_COMPILE_FLAGS 1
2796 2796
@@ -3912,10 +3912,8 @@ struct eth_rss_update_ramrod_data {
3912#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 3912#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3913#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 3913#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3914#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 3914#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3915#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6) 3915#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
3916#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6 3916#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
3917#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3918#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3919 u8 rss_result_mask; 3917 u8 rss_result_mask;
3920 u8 rss_mode; 3918 u8 rss_mode;
3921 __le32 __reserved2; 3919 __le32 __reserved2;
@@ -4131,27 +4129,29 @@ struct eth_tx_start_bd {
4131#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4129#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4132#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4130#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4133#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4131#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4134#define ETH_TX_START_BD_RESREVED (0x1<<5) 4132#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4135#define ETH_TX_START_BD_RESREVED_SHIFT 5 4133#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4136#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) 4134#define ETH_TX_START_BD_RESREVED (0x1<<7)
4137#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 4135#define ETH_TX_START_BD_RESREVED_SHIFT 7
4138}; 4136};
4139 4137
4140/* 4138/*
4141 * Tx parsing BD structure for ETH E1/E1h 4139 * Tx parsing BD structure for ETH E1/E1h
4142 */ 4140 */
4143struct eth_tx_parse_bd_e1x { 4141struct eth_tx_parse_bd_e1x {
4144 u8 global_data; 4142 __le16 global_data;
4145#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4143#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4146#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4144#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4147#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) 4145#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4148#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 4146#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4149#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) 4147#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4150#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 4148#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4151#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) 4149#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4152#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 4150#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4153#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) 4151#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4154#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 4152#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4153#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4154#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4155 u8 tcp_flags; 4155 u8 tcp_flags;
4156#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4156#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4157#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4157#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
@@ -4170,7 +4170,6 @@ struct eth_tx_parse_bd_e1x {
4170#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4170#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4171#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4171#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4172 u8 ip_hlen_w; 4172 u8 ip_hlen_w;
4173 s8 reserved;
4174 __le16 total_hlen_w; 4173 __le16 total_hlen_w;
4175 __le16 tcp_pseudo_csum; 4174 __le16 tcp_pseudo_csum;
4176 __le16 lso_mss; 4175 __le16 lso_mss;
@@ -4189,14 +4188,16 @@ struct eth_tx_parse_bd_e2 {
4189 __le16 src_mac_addr_mid; 4188 __le16 src_mac_addr_mid;
4190 __le16 src_mac_addr_hi; 4189 __le16 src_mac_addr_hi;
4191 __le32 parsing_data; 4190 __le32 parsing_data;
4192#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0) 4191#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0)
4193#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 4192#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
4194#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13) 4193#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4195#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13 4194#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4196#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17) 4195#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4197#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17 4196#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4198#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31) 4197#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4199#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31 4198#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4199#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4200#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4200}; 4201};
4201 4202
4202/* 4203/*
@@ -4964,7 +4965,8 @@ struct flow_control_configuration {
4964 * 4965 *
4965 */ 4966 */
4966struct function_start_data { 4967struct function_start_data {
4967 __le16 function_mode; 4968 u8 function_mode;
4969 u8 reserved;
4968 __le16 sd_vlan_tag; 4970 __le16 sd_vlan_tag;
4969 __le16 vif_id; 4971 __le16 vif_id;
4970 u8 path_id; 4972 u8 path_id;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
index 559c396d45cc..c8f10f0e8a0d 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
@@ -566,7 +566,7 @@ static const struct {
566 u32 e2; /* 57712 */ 566 u32 e2; /* 57712 */
567 u32 e3; /* 578xx */ 567 u32 e3; /* 578xx */
568 } reg_mask; /* Register mask (all valid bits) */ 568 } reg_mask; /* Register mask (all valid bits) */
569 char name[7]; /* Block's longest name is 6 characters long 569 char name[8]; /* Block's longest name is 7 characters long
570 * (name + suffix) 570 * (name + suffix)
571 */ 571 */
572} bnx2x_blocks_parity_data[] = { 572} bnx2x_blocks_parity_data[] = {
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index bcc112b82831..e2e45ee5df33 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -161,120 +161,6 @@
161#define EDC_MODE_LIMITING 0x0044 161#define EDC_MODE_LIMITING 0x0044
162#define EDC_MODE_PASSIVE_DAC 0x0055 162#define EDC_MODE_PASSIVE_DAC 0x0055
163 163
164/* BRB default for class 0 E2 */
165#define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
166#define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
167#define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
168#define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
169
170/* BRB thresholds for E2*/
171#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
172#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
173
174#define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
175#define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
176
177#define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
178#define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
179
180#define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
181#define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
182
183/* BRB default for class 0 E3A0 */
184#define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
185#define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
186#define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
187#define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
188
189/* BRB thresholds for E3A0 */
190#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
191#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
192
193#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
194#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
195
196#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
197#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
198
199#define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
200#define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
201
202/* BRB default for E3B0 */
203#define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
204#define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
205#define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
206#define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
207
208/* BRB thresholds for E3B0 2 port mode*/
209#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
210#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
211
212#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
213#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
214
215#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
216#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
217
218#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
219#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
220
221/* only for E3B0*/
222#define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
223#define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
224
225/* Lossy +Lossless GUARANTIED == GUART */
226#define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
227/* Lossless +Lossless*/
228#define PFC_E3B0_2P_PAUSE_LB_GUART 236
229/* Lossy +Lossy*/
230#define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
231
232/* Lossy +Lossless*/
233#define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
234/* Lossless +Lossless*/
235#define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
236/* Lossy +Lossy*/
237#define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
238#define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
239
240#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
241#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
242
243/* BRB thresholds for E3B0 4 port mode */
244#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
245#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
246
247#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
248#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
249
250#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
251#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
252
253#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
254#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
255
256/* only for E3B0*/
257#define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
258#define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
259#define PFC_E3B0_4P_LB_GUART 120
260
261#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
262#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
263
264#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
265#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
266
267/* Pause defines*/
268#define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
269#define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
270#define DEFAULT_E3B0_LB_GUART 40
271
272#define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
273#define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
274
275#define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
276#define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
277
278/* ETS defines*/ 164/* ETS defines*/
279#define DCBX_INVALID_COS (0xFF) 165#define DCBX_INVALID_COS (0xFF)
280 166
@@ -2144,391 +2030,6 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
2144 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2145} 2031}
2146 2032
2147/* PFC BRB internal port configuration params */
2148struct bnx2x_pfc_brb_threshold_val {
2149 u32 pause_xoff;
2150 u32 pause_xon;
2151 u32 full_xoff;
2152 u32 full_xon;
2153};
2154
2155struct bnx2x_pfc_brb_e3b0_val {
2156 u32 per_class_guaranty_mode;
2157 u32 lb_guarantied_hyst;
2158 u32 full_lb_xoff_th;
2159 u32 full_lb_xon_threshold;
2160 u32 lb_guarantied;
2161 u32 mac_0_class_t_guarantied;
2162 u32 mac_0_class_t_guarantied_hyst;
2163 u32 mac_1_class_t_guarantied;
2164 u32 mac_1_class_t_guarantied_hyst;
2165};
2166
2167struct bnx2x_pfc_brb_th_val {
2168 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2169 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2170 struct bnx2x_pfc_brb_threshold_val default_class0;
2171 struct bnx2x_pfc_brb_threshold_val default_class1;
2172
2173};
2174static int bnx2x_pfc_brb_get_config_params(
2175 struct link_params *params,
2176 struct bnx2x_pfc_brb_th_val *config_val)
2177{
2178 struct bnx2x *bp = params->bp;
2179 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2180
2181 config_val->default_class1.pause_xoff = 0;
2182 config_val->default_class1.pause_xon = 0;
2183 config_val->default_class1.full_xoff = 0;
2184 config_val->default_class1.full_xon = 0;
2185
2186 if (CHIP_IS_E2(bp)) {
2187 /* Class0 defaults */
2188 config_val->default_class0.pause_xoff =
2189 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2190 config_val->default_class0.pause_xon =
2191 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2192 config_val->default_class0.full_xoff =
2193 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2194 config_val->default_class0.full_xon =
2195 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2196 /* Pause able*/
2197 config_val->pauseable_th.pause_xoff =
2198 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2199 config_val->pauseable_th.pause_xon =
2200 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2201 config_val->pauseable_th.full_xoff =
2202 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2203 config_val->pauseable_th.full_xon =
2204 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2205 /* Non pause able*/
2206 config_val->non_pauseable_th.pause_xoff =
2207 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2208 config_val->non_pauseable_th.pause_xon =
2209 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2210 config_val->non_pauseable_th.full_xoff =
2211 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2212 config_val->non_pauseable_th.full_xon =
2213 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2214 } else if (CHIP_IS_E3A0(bp)) {
2215 /* Class0 defaults */
2216 config_val->default_class0.pause_xoff =
2217 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2218 config_val->default_class0.pause_xon =
2219 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2220 config_val->default_class0.full_xoff =
2221 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2222 config_val->default_class0.full_xon =
2223 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2224 /* Pause able */
2225 config_val->pauseable_th.pause_xoff =
2226 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2227 config_val->pauseable_th.pause_xon =
2228 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2229 config_val->pauseable_th.full_xoff =
2230 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2231 config_val->pauseable_th.full_xon =
2232 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2233 /* Non pause able*/
2234 config_val->non_pauseable_th.pause_xoff =
2235 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2236 config_val->non_pauseable_th.pause_xon =
2237 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2238 config_val->non_pauseable_th.full_xoff =
2239 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2240 config_val->non_pauseable_th.full_xon =
2241 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2242 } else if (CHIP_IS_E3B0(bp)) {
2243 /* Class0 defaults */
2244 config_val->default_class0.pause_xoff =
2245 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2246 config_val->default_class0.pause_xon =
2247 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2248 config_val->default_class0.full_xoff =
2249 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2250 config_val->default_class0.full_xon =
2251 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2252
2253 if (params->phy[INT_PHY].flags &
2254 FLAGS_4_PORT_MODE) {
2255 config_val->pauseable_th.pause_xoff =
2256 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2257 config_val->pauseable_th.pause_xon =
2258 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2259 config_val->pauseable_th.full_xoff =
2260 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2261 config_val->pauseable_th.full_xon =
2262 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2263 /* Non pause able*/
2264 config_val->non_pauseable_th.pause_xoff =
2265 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2266 config_val->non_pauseable_th.pause_xon =
2267 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2268 config_val->non_pauseable_th.full_xoff =
2269 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2270 config_val->non_pauseable_th.full_xon =
2271 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2272 } else {
2273 config_val->pauseable_th.pause_xoff =
2274 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2275 config_val->pauseable_th.pause_xon =
2276 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2277 config_val->pauseable_th.full_xoff =
2278 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2279 config_val->pauseable_th.full_xon =
2280 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2281 /* Non pause able*/
2282 config_val->non_pauseable_th.pause_xoff =
2283 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2284 config_val->non_pauseable_th.pause_xon =
2285 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2286 config_val->non_pauseable_th.full_xoff =
2287 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2288 config_val->non_pauseable_th.full_xon =
2289 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2290 }
2291 } else
2292 return -EINVAL;
2293
2294 return 0;
2295}
2296
2297static void bnx2x_pfc_brb_get_e3b0_config_params(
2298 struct link_params *params,
2299 struct bnx2x_pfc_brb_e3b0_val
2300 *e3b0_val,
2301 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2302 const u8 pfc_enabled)
2303{
2304 if (pfc_enabled && pfc_params) {
2305 e3b0_val->per_class_guaranty_mode = 1;
2306 e3b0_val->lb_guarantied_hyst = 80;
2307
2308 if (params->phy[INT_PHY].flags &
2309 FLAGS_4_PORT_MODE) {
2310 e3b0_val->full_lb_xoff_th =
2311 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2312 e3b0_val->full_lb_xon_threshold =
2313 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2314 e3b0_val->lb_guarantied =
2315 PFC_E3B0_4P_LB_GUART;
2316 e3b0_val->mac_0_class_t_guarantied =
2317 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2318 e3b0_val->mac_0_class_t_guarantied_hyst =
2319 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2320 e3b0_val->mac_1_class_t_guarantied =
2321 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2322 e3b0_val->mac_1_class_t_guarantied_hyst =
2323 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2324 } else {
2325 e3b0_val->full_lb_xoff_th =
2326 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2327 e3b0_val->full_lb_xon_threshold =
2328 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2329 e3b0_val->mac_0_class_t_guarantied_hyst =
2330 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2331 e3b0_val->mac_1_class_t_guarantied =
2332 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2333 e3b0_val->mac_1_class_t_guarantied_hyst =
2334 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2335
2336 if (pfc_params->cos0_pauseable !=
2337 pfc_params->cos1_pauseable) {
2338 /* Nonpauseable= Lossy + pauseable = Lossless*/
2339 e3b0_val->lb_guarantied =
2340 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2341 e3b0_val->mac_0_class_t_guarantied =
2342 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2343 } else if (pfc_params->cos0_pauseable) {
2344 /* Lossless +Lossless*/
2345 e3b0_val->lb_guarantied =
2346 PFC_E3B0_2P_PAUSE_LB_GUART;
2347 e3b0_val->mac_0_class_t_guarantied =
2348 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2349 } else {
2350 /* Lossy +Lossy*/
2351 e3b0_val->lb_guarantied =
2352 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2353 e3b0_val->mac_0_class_t_guarantied =
2354 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2355 }
2356 }
2357 } else {
2358 e3b0_val->per_class_guaranty_mode = 0;
2359 e3b0_val->lb_guarantied_hyst = 0;
2360 e3b0_val->full_lb_xoff_th =
2361 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2362 e3b0_val->full_lb_xon_threshold =
2363 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2364 e3b0_val->lb_guarantied =
2365 DEFAULT_E3B0_LB_GUART;
2366 e3b0_val->mac_0_class_t_guarantied =
2367 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2368 e3b0_val->mac_0_class_t_guarantied_hyst =
2369 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2370 e3b0_val->mac_1_class_t_guarantied =
2371 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2372 e3b0_val->mac_1_class_t_guarantied_hyst =
2373 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2374 }
2375}
2376static int bnx2x_update_pfc_brb(struct link_params *params,
2377 struct link_vars *vars,
2378 struct bnx2x_nig_brb_pfc_port_params
2379 *pfc_params)
2380{
2381 struct bnx2x *bp = params->bp;
2382 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2383 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2384 &config_val.pauseable_th;
2385 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2386 const int set_pfc = params->feature_config_flags &
2387 FEATURE_CONFIG_PFC_ENABLED;
2388 const u8 pfc_enabled = (set_pfc && pfc_params);
2389 int bnx2x_status = 0;
2390 u8 port = params->port;
2391
2392 /* default - pause configuration */
2393 reg_th_config = &config_val.pauseable_th;
2394 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2395 if (bnx2x_status)
2396 return bnx2x_status;
2397
2398 if (pfc_enabled) {
2399 /* First COS */
2400 if (pfc_params->cos0_pauseable)
2401 reg_th_config = &config_val.pauseable_th;
2402 else
2403 reg_th_config = &config_val.non_pauseable_th;
2404 } else
2405 reg_th_config = &config_val.default_class0;
2406 /* The number of free blocks below which the pause signal to class 0
2407 * of MAC #n is asserted. n=0,1
2408 */
2409 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2410 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2411 reg_th_config->pause_xoff);
2412 /* The number of free blocks above which the pause signal to class 0
2413 * of MAC #n is de-asserted. n=0,1
2414 */
2415 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2416 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2417 /* The number of free blocks below which the full signal to class 0
2418 * of MAC #n is asserted. n=0,1
2419 */
2420 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2421 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2422 /* The number of free blocks above which the full signal to class 0
2423 * of MAC #n is de-asserted. n=0,1
2424 */
2425 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2426 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2427
2428 if (pfc_enabled) {
2429 /* Second COS */
2430 if (pfc_params->cos1_pauseable)
2431 reg_th_config = &config_val.pauseable_th;
2432 else
2433 reg_th_config = &config_val.non_pauseable_th;
2434 } else
2435 reg_th_config = &config_val.default_class1;
2436 /* The number of free blocks below which the pause signal to
2437 * class 1 of MAC #n is asserted. n=0,1
2438 */
2439 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2440 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2441 reg_th_config->pause_xoff);
2442
2443 /* The number of free blocks above which the pause signal to
2444 * class 1 of MAC #n is de-asserted. n=0,1
2445 */
2446 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2447 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2448 reg_th_config->pause_xon);
2449 /* The number of free blocks below which the full signal to
2450 * class 1 of MAC #n is asserted. n=0,1
2451 */
2452 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2453 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2454 reg_th_config->full_xoff);
2455 /* The number of free blocks above which the full signal to
2456 * class 1 of MAC #n is de-asserted. n=0,1
2457 */
2458 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2459 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2460 reg_th_config->full_xon);
2461
2462 if (CHIP_IS_E3B0(bp)) {
2463 bnx2x_pfc_brb_get_e3b0_config_params(
2464 params,
2465 &e3b0_val,
2466 pfc_params,
2467 pfc_enabled);
2468
2469 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2470 e3b0_val.per_class_guaranty_mode);
2471
2472 /* The hysteresis on the guarantied buffer space for the Lb
2473 * port before signaling XON.
2474 */
2475 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2476 e3b0_val.lb_guarantied_hyst);
2477
2478 /* The number of free blocks below which the full signal to the
2479 * LB port is asserted.
2480 */
2481 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2482 e3b0_val.full_lb_xoff_th);
2483 /* The number of free blocks above which the full signal to the
2484 * LB port is de-asserted.
2485 */
2486 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2487 e3b0_val.full_lb_xon_threshold);
2488 /* The number of blocks guarantied for the MAC #n port. n=0,1
2489 */
2490
2491 /* The number of blocks guarantied for the LB port. */
2492 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2493 e3b0_val.lb_guarantied);
2494
2495 /* The number of blocks guarantied for the MAC #n port. */
2496 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2497 2 * e3b0_val.mac_0_class_t_guarantied);
2498 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2499 2 * e3b0_val.mac_1_class_t_guarantied);
2500 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2501 */
2502 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2503 e3b0_val.mac_0_class_t_guarantied);
2504 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2505 e3b0_val.mac_0_class_t_guarantied);
2506 /* The hysteresis on the guarantied buffer space for class in
2507 * MAC0. t=0,1
2508 */
2509 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2510 e3b0_val.mac_0_class_t_guarantied_hyst);
2511 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2512 e3b0_val.mac_0_class_t_guarantied_hyst);
2513
2514 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2515 */
2516 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2517 e3b0_val.mac_1_class_t_guarantied);
2518 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2519 e3b0_val.mac_1_class_t_guarantied);
2520 /* The hysteresis on the guarantied buffer space for class #t
2521 * in MAC1. t=0,1
2522 */
2523 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2524 e3b0_val.mac_1_class_t_guarantied_hyst);
2525 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2526 e3b0_val.mac_1_class_t_guarantied_hyst);
2527 }
2528
2529 return bnx2x_status;
2530}
2531
2532/****************************************************************************** 2033/******************************************************************************
2533* Description: 2034* Description:
2534* This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2035* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
@@ -2705,11 +2206,6 @@ int bnx2x_update_pfc(struct link_params *params,
2705 /* Update NIG params */ 2206 /* Update NIG params */
2706 bnx2x_update_pfc_nig(params, vars, pfc_params); 2207 bnx2x_update_pfc_nig(params, vars, pfc_params);
2707 2208
2708 /* Update BRB params */
2709 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2710 if (bnx2x_status)
2711 return bnx2x_status;
2712
2713 if (!vars->link_up) 2209 if (!vars->link_up)
2714 return bnx2x_status; 2210 return bnx2x_status;
2715 2211
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index 5a5fbf57c4b4..71971a161bd1 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -5619,7 +5619,7 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
5619 memset(rdata, 0, sizeof(*rdata)); 5619 memset(rdata, 0, sizeof(*rdata));
5620 5620
5621 /* Fill the ramrod data with provided parameters */ 5621 /* Fill the ramrod data with provided parameters */
5622 rdata->function_mode = cpu_to_le16(start_params->mf_mode); 5622 rdata->function_mode = (u8)start_params->mf_mode;
5623 rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); 5623 rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
5624 rdata->path_id = BP_PATH(bp); 5624 rdata->path_id = BP_PATH(bp);
5625 rdata->network_cos_mode = start_params->network_cos_mode; 5625 rdata->network_cos_mode = start_params->network_cos_mode;
diff --git a/drivers/net/ethernet/broadcom/cnic.c b/drivers/net/ethernet/broadcom/cnic.c
index 2107d79d69b3..cc8434fd606e 100644
--- a/drivers/net/ethernet/broadcom/cnic.c
+++ b/drivers/net/ethernet/broadcom/cnic.c
@@ -4891,6 +4891,9 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4891 buf_map = udev->l2_buf_map; 4891 buf_map = udev->l2_buf_map;
4892 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) { 4892 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4893 struct eth_tx_start_bd *start_bd = &txbd->start_bd; 4893 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4894 struct eth_tx_parse_bd_e1x *pbd_e1x =
4895 &((txbd + 1)->parse_bd_e1x);
4896 struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
4894 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd); 4897 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4895 4898
4896 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32); 4899 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
@@ -4900,10 +4903,15 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4900 start_bd->nbytes = cpu_to_le16(0x10); 4903 start_bd->nbytes = cpu_to_le16(0x10);
4901 start_bd->nbd = cpu_to_le16(3); 4904 start_bd->nbd = cpu_to_le16(3);
4902 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 4905 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4903 start_bd->general_data = (UNICAST_ADDRESS << 4906 start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
4904 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
4905 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT); 4907 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4906 4908
4909 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
4910 pbd_e2->parsing_data = (UNICAST_ADDRESS <<
4911 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
4912 else
4913 pbd_e1x->global_data = (UNICAST_ADDRESS <<
4914 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
4907 } 4915 }
4908 4916
4909 val = (u64) ring_map >> 32; 4917 val = (u64) ring_map >> 32;
diff --git a/drivers/net/ethernet/broadcom/cnic_defs.h b/drivers/net/ethernet/broadcom/cnic_defs.h
index 382c98b0cc0c..ede3db35d757 100644
--- a/drivers/net/ethernet/broadcom/cnic_defs.h
+++ b/drivers/net/ethernet/broadcom/cnic_defs.h
@@ -896,7 +896,7 @@ struct tstorm_tcp_tcp_ag_context_section {
896 u32 snd_nxt; 896 u32 snd_nxt;
897 u32 rtt_seq; 897 u32 rtt_seq;
898 u32 rtt_time; 898 u32 rtt_time;
899 u32 __reserved66; 899 u32 wnd_right_edge_local;
900 u32 wnd_right_edge; 900 u32 wnd_right_edge;
901 u32 tcp_agg_vars1; 901 u32 tcp_agg_vars1;
902#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) 902#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
diff --git a/drivers/net/ethernet/broadcom/cnic_if.h b/drivers/net/ethernet/broadcom/cnic_if.h
index 2e92c348083e..865095aad1f6 100644
--- a/drivers/net/ethernet/broadcom/cnic_if.h
+++ b/drivers/net/ethernet/broadcom/cnic_if.h
@@ -14,8 +14,8 @@
14 14
15#include "bnx2x/bnx2x_mfw_req.h" 15#include "bnx2x/bnx2x_mfw_req.h"
16 16
17#define CNIC_MODULE_VERSION "2.5.13" 17#define CNIC_MODULE_VERSION "2.5.14"
18#define CNIC_MODULE_RELDATE "Sep 07, 2012" 18#define CNIC_MODULE_RELDATE "Sep 30, 2012"
19 19
20#define CNIC_ULP_RDMA 0 20#define CNIC_ULP_RDMA 0
21#define CNIC_ULP_ISCSI 1 21#define CNIC_ULP_ISCSI 1
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 12:53:54 -0400