dma: MIC X100 DMA Driver

This patch implements DMA Engine API for DMA controller on MIC X100
Coprocessors. DMA h/w is shared between host and card s/w.
Channels 0 to 3 are used by host and 4 to 7 are used by card.
Since the DMA device doesn't show up as PCIe device, a virtual bus called mic
bus is created and virtual devices are added on that bus to follow device model.
Allowed dma transfer directions are host to card, card to host and card to card.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Nikhil Rao <nikhil.rao@intel.com>
Reviewed-by: Sudeep Dutt <sudeep.dutt@intel.com>
Signed-off-by: Siva Yerramreddy <yshivakrishna@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

4 files changed, 1080 insertions, 0 deletions

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 1eca7b9760e6..7c8b8c41f4f4 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -33,6 +33,25 @@ if DMADEVICES
 
 comment "DMA Devices"
 
+config INTEL_MIC_X100_DMA
+        tristate "Intel MIC X100 DMA Driver"
+        depends on 64BIT && X86 && INTEL_MIC_BUS
+        select DMAENGINE
+        default N
+        help
+          This enables DMA support for the Intel Many Integrated Core
+          (MIC) family of PCIe form factor coprocessor X100 devices that
+          run a 64 bit Linux OS. This driver will be used by both MIC
+          host and card drivers.
+
+          If you are building host kernel with a MIC device or a card
+          kernel for a MIC device, then say M (recommended) or Y, else
+          say N. If unsure say N.
+
+          More information about the Intel MIC family as well as the Linux
+          OS and tools for MIC to use with this driver are available from
+          <http://software.intel.com/en-us/mic-developer>.
+
 config INTEL_MID_DMAC
         tristate "Intel MID DMA support for Peripheral DMA controllers"
         depends on PCI && X86
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index c779e1eb2db2..bd9e7fa928bd 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
 obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
 obj-y += xilinx/
+obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
diff --git a/drivers/dma/mic_x100_dma.c b/drivers/dma/mic_x100_dma.c
new file mode 100644
index 000000000000..6de2e677be04
--- /dev/null
+++ b/drivers/dma/mic_x100_dma.c
@@ -0,0 +1,774 @@
+/*
+ * Intel MIC Platform Software Stack (MPSS)
+ *
+ * Copyright(c) 2014 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * Intel MIC X100 DMA Driver.
+ *
+ * Adapted from IOAT dma driver.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/seq_file.h>
+
+#include "mic_x100_dma.h"
+
+#define MIC_DMA_MAX_XFER_SIZE_CARD  (1 * 1024 * 1024 -\
+                                       MIC_DMA_ALIGN_BYTES)
+#define MIC_DMA_MAX_XFER_SIZE_HOST  (1 * 1024 * 1024 >> 1)
+#define MIC_DMA_DESC_TYPE_SHIFT 60
+#define MIC_DMA_MEMCPY_LEN_SHIFT 46
+#define MIC_DMA_STAT_INTR_SHIFT 59
+
+/* high-water mark for pushing dma descriptors */
+static int mic_dma_pending_level = 4;
+
+/* Status descriptor is used to write a 64 bit value to a memory location */
+enum mic_dma_desc_format_type {
+        MIC_DMA_MEMCPY = 1,
+        MIC_DMA_STATUS,
+};
+
+static inline u32 mic_dma_hw_ring_inc(u32 val)
+{
+        return (val + 1) % MIC_DMA_DESC_RX_SIZE;
+}
+
+static inline u32 mic_dma_hw_ring_dec(u32 val)
+{
+        return val ? val - 1 : MIC_DMA_DESC_RX_SIZE - 1;
+}
+
+static inline void mic_dma_hw_ring_inc_head(struct mic_dma_chan *ch)
+{
+        ch->head = mic_dma_hw_ring_inc(ch->head);
+}
+
+/* Prepare a memcpy desc */
+static inline void mic_dma_memcpy_desc(struct mic_dma_desc *desc,
+        dma_addr_t src_phys, dma_addr_t dst_phys, u64 size)
+{
+        u64 qw0, qw1;
+
+        qw0 = src_phys;
+        qw0 |= (size >> MIC_DMA_ALIGN_SHIFT) << MIC_DMA_MEMCPY_LEN_SHIFT;
+        qw1 = MIC_DMA_MEMCPY;
+        qw1 <<= MIC_DMA_DESC_TYPE_SHIFT;
+        qw1 |= dst_phys;
+        desc->qw0 = qw0;
+        desc->qw1 = qw1;
+}
+
+/* Prepare a status desc. with @data to be written at @dst_phys */
+static inline void mic_dma_prep_status_desc(struct mic_dma_desc *desc, u64 data,
+        dma_addr_t dst_phys, bool generate_intr)
+{
+        u64 qw0, qw1;
+
+        qw0 = data;
+        qw1 = (u64) MIC_DMA_STATUS << MIC_DMA_DESC_TYPE_SHIFT | dst_phys;
+        if (generate_intr)
+                qw1 |= (1ULL << MIC_DMA_STAT_INTR_SHIFT);
+        desc->qw0 = qw0;
+        desc->qw1 = qw1;
+}
+
+static void mic_dma_cleanup(struct mic_dma_chan *ch)
+{
+        struct dma_async_tx_descriptor *tx;
+        u32 tail;
+        u32 last_tail;
+
+        spin_lock(&ch->cleanup_lock);
+        tail = mic_dma_read_cmp_cnt(ch);
+        /*
+         * This is the barrier pair for smp_wmb() in fn.
+         * mic_dma_tx_submit_unlock. It's required so that we read the
+         * updated cookie value from tx->cookie.
+         */
+        smp_rmb();
+        for (last_tail = ch->last_tail; tail != last_tail;) {
+                tx = &ch->tx_array[last_tail];
+                if (tx->cookie) {
+                        dma_cookie_complete(tx);
+                        if (tx->callback) {
+                                tx->callback(tx->callback_param);
+                                tx->callback = NULL;
+                        }
+                }
+                last_tail = mic_dma_hw_ring_inc(last_tail);
+        }
+        /* finish all completion callbacks before incrementing tail */
+        smp_mb();
+        ch->last_tail = last_tail;
+        spin_unlock(&ch->cleanup_lock);
+}
+
+static u32 mic_dma_ring_count(u32 head, u32 tail)
+{
+        u32 count;
+
+        if (head >= tail)
+                count = (tail - 0) + (MIC_DMA_DESC_RX_SIZE - head);
+        else
+                count = tail - head;
+        return count - 1;
+}
+
+/* Returns the num. of free descriptors on success, -ENOMEM on failure */
+static int mic_dma_avail_desc_ring_space(struct mic_dma_chan *ch, int required)
+{
+        struct device *dev = mic_dma_ch_to_device(ch);
+        u32 count;
+
+        count = mic_dma_ring_count(ch->head, ch->last_tail);
+        if (count < required) {
+                mic_dma_cleanup(ch);
+                count = mic_dma_ring_count(ch->head, ch->last_tail);
+        }
+
+        if (count < required) {
+                dev_dbg(dev, "Not enough desc space");
+                dev_dbg(dev, "%s %d required=%u, avail=%u\n",
+                        __func__, __LINE__, required, count);
+                return -ENOMEM;
+        } else {
+                return count;
+        }
+}
+
+/* Program memcpy descriptors into the descriptor ring and update s/w head ptr*/
+static int mic_dma_prog_memcpy_desc(struct mic_dma_chan *ch, dma_addr_t src,
+                                    dma_addr_t dst, size_t len)