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authorJamie Iles <jamie@jamieiles.com>2011-05-06 10:28:56 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2011-05-24 21:02:01 -0400
commit9589bf5bed2936a159fc96c96339f15a512fdfa9 (patch)
treeca0547147e34fc91ba7112c00315fd518dbfa16a
parent84457949e4921f15548a9d317a4a4318b3c3af75 (diff)
mtd: denali: remove nearly-duplicated register definitions
The controller has interrupt enable/status register pairs for each bank (along with ECC and status registers) that differ only in address offset. Rather than providing definitions for each register, make the address a macro so that it scales for devices with different numbers of banks. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat
-rw-r--r--drivers/mtd/nand/denali.c134
-rw-r--r--drivers/mtd/nand/denali.h371
2 files changed, 110 insertions, 395 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 3184eb9bdd57..5568640cb3ba 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -45,16 +45,16 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
45 45
46/* We define a macro here that combines all interrupts this driver uses into 46/* We define a macro here that combines all interrupts this driver uses into
47 * a single constant value, for convenience. */ 47 * a single constant value, for convenience. */
48#define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \ 48#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
49 INTR_STATUS0__ECC_TRANSACTION_DONE | \ 49 INTR_STATUS__ECC_TRANSACTION_DONE | \
50 INTR_STATUS0__ECC_ERR | \ 50 INTR_STATUS__ECC_ERR | \
51 INTR_STATUS0__PROGRAM_FAIL | \ 51 INTR_STATUS__PROGRAM_FAIL | \
52 INTR_STATUS0__LOAD_COMP | \ 52 INTR_STATUS__LOAD_COMP | \
53 INTR_STATUS0__PROGRAM_COMP | \ 53 INTR_STATUS__PROGRAM_COMP | \
54 INTR_STATUS0__TIME_OUT | \ 54 INTR_STATUS__TIME_OUT | \
55 INTR_STATUS0__ERASE_FAIL | \ 55 INTR_STATUS__ERASE_FAIL | \
56 INTR_STATUS0__RST_COMP | \ 56 INTR_STATUS__RST_COMP | \
57 INTR_STATUS0__ERASE_COMP) 57 INTR_STATUS__ERASE_COMP)
58 58
59/* indicates whether or not the internal value for the flash bank is 59/* indicates whether or not the internal value for the flash bank is
60 * valid or not */ 60 * valid or not */
@@ -96,30 +96,6 @@ static const struct pci_device_id denali_pci_ids[] = {
96 { /* end: all zeroes */ } 96 { /* end: all zeroes */ }
97}; 97};
98 98
99
100/* these are static lookup tables that give us easy access to
101 * registers in the NAND controller.
102 */
103static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
104 INTR_STATUS1,
105 INTR_STATUS2,
106 INTR_STATUS3};
107
108static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
109 DEVICE_RESET__BANK1,
110 DEVICE_RESET__BANK2,
111 DEVICE_RESET__BANK3};
112
113static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
114 INTR_STATUS1__TIME_OUT,
115 INTR_STATUS2__TIME_OUT,
116 INTR_STATUS3__TIME_OUT};
117
118static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
119 INTR_STATUS1__RST_COMP,
120 INTR_STATUS2__RST_COMP,
121 INTR_STATUS3__RST_COMP};
122
123/* forward declarations */ 99/* forward declarations */
124static void clear_interrupts(struct denali_nand_info *denali); 100static void clear_interrupts(struct denali_nand_info *denali);
125static uint32_t wait_for_irq(struct denali_nand_info *denali, 101static uint32_t wait_for_irq(struct denali_nand_info *denali,
@@ -181,18 +157,16 @@ static void read_status(struct denali_nand_info *denali)
181static void reset_bank(struct denali_nand_info *denali) 157static void reset_bank(struct denali_nand_info *denali)
182{ 158{
183 uint32_t irq_status = 0; 159 uint32_t irq_status = 0;
184 uint32_t irq_mask = reset_complete[denali->flash_bank] | 160 uint32_t irq_mask = INTR_STATUS__RST_COMP |
185 operation_timeout[denali->flash_bank]; 161 INTR_STATUS__TIME_OUT;
186 int bank = 0;
187 162
188 clear_interrupts(denali); 163 clear_interrupts(denali);
189 164
190 bank = device_reset_banks[denali->flash_bank]; 165 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
191 iowrite32(bank, denali->flash_reg + DEVICE_RESET);
192 166
193 irq_status = wait_for_irq(denali, irq_mask); 167 irq_status = wait_for_irq(denali, irq_mask);
194 168
195 if (irq_status & operation_timeout[denali->flash_bank]) 169 if (irq_status & INTR_STATUS__TIME_OUT)
196 dev_err(denali->dev, "reset bank failed.\n"); 170 dev_err(denali->dev, "reset bank failed.\n");
197} 171}
198 172
@@ -205,25 +179,24 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
205 __FILE__, __LINE__, __func__); 179 __FILE__, __LINE__, __func__);
206 180
207 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) 181 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
208 iowrite32(reset_complete[i] | operation_timeout[i], 182 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
209 denali->flash_reg + intr_status_addresses[i]); 183 denali->flash_reg + INTR_STATUS(i));
210 184
211 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) { 185 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
212 iowrite32(device_reset_banks[i], 186 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
213 denali->flash_reg + DEVICE_RESET);
214 while (!(ioread32(denali->flash_reg + 187 while (!(ioread32(denali->flash_reg +
215 intr_status_addresses[i]) & 188 INTR_STATUS(i)) &
216 (reset_complete[i] | operation_timeout[i]))) 189 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
217 cpu_relax(); 190 cpu_relax();
218 if (ioread32(denali->flash_reg + intr_status_addresses[i]) & 191 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
219 operation_timeout[i]) 192 INTR_STATUS__TIME_OUT)
220 dev_dbg(denali->dev, 193 dev_dbg(denali->dev,
221 "NAND Reset operation timed out on bank %d\n", i); 194 "NAND Reset operation timed out on bank %d\n", i);
222 } 195 }
223 196
224 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) 197 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
225 iowrite32(reset_complete[i] | operation_timeout[i], 198 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
226 denali->flash_reg + intr_status_addresses[i]); 199 denali->flash_reg + INTR_STATUS(i));
227 200
228 return PASS; 201 return PASS;
229} 202}
@@ -481,15 +454,15 @@ static void detect_partition_feature(struct denali_nand_info *denali)
481 * blocks it can't touch. 454 * blocks it can't touch.
482 * */ 455 * */
483 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { 456 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
484 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) & 457 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
485 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) { 458 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
486 denali->fwblks = 459 denali->fwblks =
487 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & 460 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
488 MIN_MAX_BANK_1__MIN_VALUE) * 461 MIN_MAX_BANK__MIN_VALUE) *
489 denali->blksperchip) 462 denali->blksperchip)
490 + 463 +
491 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) & 464 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
492 MIN_BLK_ADDR_1__VALUE); 465 MIN_BLK_ADDR__VALUE);
493 } else 466 } else
494 denali->fwblks = SPECTRA_START_BLOCK; 467 denali->fwblks = SPECTRA_START_BLOCK;
495 } else 468 } else
@@ -581,6 +554,7 @@ static inline bool is_flash_bank_valid(int flash_bank)
581static void denali_irq_init(struct denali_nand_info *denali) 554static void denali_irq_init(struct denali_nand_info *denali)
582{ 555{
583 uint32_t int_mask = 0; 556 uint32_t int_mask = 0;
557 int i;
584 558
585 /* Disable global interrupts */ 559 /* Disable global interrupts */
586 denali_set_intr_modes(denali, false); 560 denali_set_intr_modes(denali, false);
@@ -588,10 +562,8 @@ static void denali_irq_init(struct denali_nand_info *denali)
588 int_mask = DENALI_IRQ_ALL; 562 int_mask = DENALI_IRQ_ALL;
589 563
590 /* Clear all status bits */ 564 /* Clear all status bits */
591 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS0); 565 for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i)
592 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS1); 566 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
593 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS2);
594 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS3);
595 567
596 denali_irq_enable(denali, int_mask); 568 denali_irq_enable(denali, int_mask);
597} 569}
@@ -605,10 +577,10 @@ static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
605static void denali_irq_enable(struct denali_nand_info *denali, 577static void denali_irq_enable(struct denali_nand_info *denali,
606 uint32_t int_mask) 578 uint32_t int_mask)
607{ 579{
608 iowrite32(int_mask, denali->flash_reg + INTR_EN0); 580 int i;
609 iowrite32(int_mask, denali->flash_reg + INTR_EN1); 581
610 iowrite32(int_mask, denali->flash_reg + INTR_EN2); 582 for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i)
611 iowrite32(int_mask, denali->flash_reg + INTR_EN3); 583 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
612} 584}
613 585
614/* This function only returns when an interrupt that this driver cares about 586/* This function only returns when an interrupt that this driver cares about
@@ -625,7 +597,7 @@ static inline void clear_interrupt(struct denali_nand_info *denali,
625{ 597{
626 uint32_t intr_status_reg = 0; 598 uint32_t intr_status_reg = 0;
627 599
628 intr_status_reg = intr_status_addresses[denali->flash_bank]; 600 intr_status_reg = INTR_STATUS(denali->flash_bank);
629 601
630 iowrite32(irq_mask, denali->flash_reg + intr_status_reg); 602 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
631} 603}
@@ -646,7 +618,7 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali)
646{ 618{
647 uint32_t intr_status_reg = 0; 619 uint32_t intr_status_reg = 0;
648 620
649 intr_status_reg = intr_status_addresses[denali->flash_bank]; 621 intr_status_reg = INTR_STATUS(denali->flash_bank);
650 622
651 return ioread32(denali->flash_reg + intr_status_reg); 623 return ioread32(denali->flash_reg + intr_status_reg);
652} 624}
@@ -755,7 +727,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
755 irq_mask = 0; 727 irq_mask = 0;
756 728
757 if (op == DENALI_READ) 729 if (op == DENALI_READ)
758 irq_mask = INTR_STATUS0__LOAD_COMP; 730 irq_mask = INTR_STATUS__LOAD_COMP;
759 else if (op == DENALI_WRITE) 731 else if (op == DENALI_WRITE)
760 irq_mask = 0; 732 irq_mask = 0;
761 else 733 else
@@ -862,8 +834,8 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
862{ 834{
863 struct denali_nand_info *denali = mtd_to_denali(mtd); 835 struct denali_nand_info *denali = mtd_to_denali(mtd);
864 uint32_t irq_status = 0; 836 uint32_t irq_status = 0;
865 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP | 837 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
866 INTR_STATUS0__PROGRAM_FAIL; 838 INTR_STATUS__PROGRAM_FAIL;
867 int status = 0; 839 int status = 0;
868 840
869 denali->page = page; 841 denali->page = page;
@@ -890,7 +862,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
890static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) 862static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
891{ 863{
892 struct denali_nand_info *denali = mtd_to_denali(mtd); 864 struct denali_nand_info *denali = mtd_to_denali(mtd);
893 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP, 865 uint32_t irq_mask = INTR_STATUS__LOAD_COMP,
894 irq_status = 0, addr = 0x0, cmd = 0x0; 866 irq_status = 0, addr = 0x0, cmd = 0x0;
895 867
896 denali->page = page; 868 denali->page = page;
@@ -945,7 +917,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
945{ 917{
946 bool check_erased_page = false; 918 bool check_erased_page = false;
947 919
948 if (irq_status & INTR_STATUS0__ECC_ERR) { 920 if (irq_status & INTR_STATUS__ECC_ERR) {
949 /* read the ECC errors. we'll ignore them for now */ 921 /* read the ECC errors. we'll ignore them for now */
950 uint32_t err_address = 0, err_correction_info = 0; 922 uint32_t err_address = 0, err_correction_info = 0;
951 uint32_t err_byte = 0, err_sector = 0, err_device = 0; 923 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
@@ -996,7 +968,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
996 * for a while for this interrupt 968 * for a while for this interrupt
997 * */ 969 * */
998 while (!(read_interrupt_status(denali) & 970 while (!(read_interrupt_status(denali) &
999 INTR_STATUS0__ECC_TRANSACTION_DONE)) 971 INTR_STATUS__ECC_TRANSACTION_DONE))
1000 cpu_relax(); 972 cpu_relax();
1001 clear_interrupts(denali); 973 clear_interrupts(denali);
1002 denali_set_intr_modes(denali, true); 974 denali_set_intr_modes(denali, true);
@@ -1051,8 +1023,8 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1051 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1023 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1052 1024
1053 uint32_t irq_status = 0; 1025 uint32_t irq_status = 0;
1054 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP | 1026 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1055 INTR_STATUS0__PROGRAM_FAIL; 1027 INTR_STATUS__PROGRAM_FAIL;
1056 1028
1057 /* if it is a raw xfer, we want to disable ecc, and send 1029 /* if it is a raw xfer, we want to disable ecc, and send
1058 * the spare area. 1030 * the spare area.
@@ -1086,7 +1058,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1086 "timeout on write_page (type = %d)\n", 1058 "timeout on write_page (type = %d)\n",
1087 raw_xfer); 1059 raw_xfer);
1088 denali->status = 1060 denali->status =
1089 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? 1061 (irq_status & INTR_STATUS__PROGRAM_FAIL) ?
1090 NAND_STATUS_FAIL : PASS; 1062 NAND_STATUS_FAIL : PASS;
1091 } 1063 }
1092 1064
@@ -1144,8 +1116,8 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1144 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1116 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1145 1117
1146 uint32_t irq_status = 0; 1118 uint32_t irq_status = 0;
1147 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE | 1119 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1148 INTR_STATUS0__ECC_ERR; 1120 INTR_STATUS__ECC_ERR;
1149 bool check_erased_page = false; 1121 bool check_erased_page = false;
1150 1122
1151 if (page != denali->page) { 1123 if (page != denali->page) {
@@ -1196,7 +1168,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1196 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1168 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1197 1169
1198 uint32_t irq_status = 0; 1170 uint32_t irq_status = 0;
1199 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; 1171 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1200 1172
1201 if (page != denali->page) { 1173 if (page != denali->page) {
1202 dev_err(denali->dev, "IN %s: page %d is not" 1174 dev_err(denali->dev, "IN %s: page %d is not"
@@ -1269,10 +1241,10 @@ static void denali_erase(struct mtd_info *mtd, int page)
1269 index_addr(denali, (uint32_t)cmd, 0x1); 1241 index_addr(denali, (uint32_t)cmd, 0x1);
1270 1242
1271 /* wait for erase to complete or failure to occur */ 1243 /* wait for erase to complete or failure to occur */
1272 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP | 1244 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1273 INTR_STATUS0__ERASE_FAIL); 1245 INTR_STATUS__ERASE_FAIL);
1274 1246
1275 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? 1247 denali->status = (irq_status & INTR_STATUS__ERASE_FAIL) ?
1276 NAND_STATUS_FAIL : PASS; 1248 NAND_STATUS_FAIL : PASS;
1277} 1249}
1278 1250
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index 9b875fd23687..638668c4b41f 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -211,185 +211,46 @@
211#define TRANSFER_MODE 0x400 211#define TRANSFER_MODE 0x400
212#define TRANSFER_MODE__VALUE 0x0003 212#define TRANSFER_MODE__VALUE 0x0003
213 213
214#define INTR_STATUS0 0x410 214#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
215#define INTR_STATUS0__ECC_TRANSACTION_DONE 0x0001 215#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
216#define INTR_STATUS0__ECC_ERR 0x0002 216
217#define INTR_STATUS0__DMA_CMD_COMP 0x0004 217#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001
218#define INTR_STATUS0__TIME_OUT 0x0008 218#define INTR_STATUS__ECC_ERR 0x0002
219#define INTR_STATUS0__PROGRAM_FAIL 0x0010 219#define INTR_STATUS__DMA_CMD_COMP 0x0004
220#define INTR_STATUS0__ERASE_FAIL 0x0020 220#define INTR_STATUS__TIME_OUT 0x0008
221#define INTR_STATUS0__LOAD_COMP 0x0040 221#define INTR_STATUS__PROGRAM_FAIL 0x0010
222#define INTR_STATUS0__PROGRAM_COMP 0x0080 222#define INTR_STATUS__ERASE_FAIL 0x0020
223#define INTR_STATUS0__ERASE_COMP 0x0100 223#define INTR_STATUS__LOAD_COMP 0x0040
224#define INTR_STATUS0__PIPE_CPYBCK_CMD_COMP 0x0200 224#define INTR_STATUS__PROGRAM_COMP 0x0080
225#define INTR_STATUS0__LOCKED_BLK 0x0400 225#define INTR_STATUS__ERASE_COMP 0x0100
226#define INTR_STATUS0__UNSUP_CMD 0x0800 226#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
227#define INTR_STATUS0__INT_ACT 0x1000 227#define INTR_STATUS__LOCKED_BLK 0x0400
228#define INTR_STATUS0__RST_COMP 0x2000 228#define INTR_STATUS__UNSUP_CMD 0x0800
229#define INTR_STATUS0__PIPE_CMD_ERR 0x4000 229#define INTR_STATUS__INT_ACT 0x1000
230#define INTR_STATUS0__PAGE_XFER_INC 0x8000 230#define INTR_STATUS__RST_COMP 0x2000
231 231#define INTR_STATUS__PIPE_CMD_ERR 0x4000
232#define INTR_EN0 0x420 232#define INTR_STATUS__PAGE_XFER_INC 0x8000
233#define INTR_EN0__ECC_TRANSACTION_DONE 0x0001 233
234#define INTR_EN0__ECC_ERR 0x0002 234#define INTR_EN__ECC_TRANSACTION_DONE 0x0001
235#define INTR_EN0__DMA_CMD_COMP 0x0004 235#define INTR_EN__ECC_ERR 0x0002
236#define INTR_EN0__TIME_OUT 0x0008 236#define INTR_EN__DMA_CMD_COMP 0x0004
237#define INTR_EN0__PROGRAM_FAIL 0x0010 237#define INTR_EN__TIME_OUT 0x0008
238#define INTR_EN0__ERASE_FAIL 0x0020 238#define INTR_EN__PROGRAM_FAIL 0x0010
239#define INTR_EN0__LOAD_COMP 0x0040 239#define INTR_EN__ERASE_FAIL 0x0020
240#define INTR_EN0__PROGRAM_COMP 0x0080 240#define INTR_EN__LOAD_COMP 0x0040
241#define INTR_EN0__ERASE_COMP 0x0100 241#define INTR_EN__PROGRAM_COMP 0x0080
242#define INTR_EN0__PIPE_CPYBCK_CMD_COMP 0x0200 242#define INTR_EN__ERASE_COMP 0x0100
243#define INTR_EN0__LOCKED_BLK 0x0400 243#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
244#define INTR_EN0__UNSUP_CMD 0x0800 244#define INTR_EN__LOCKED_BLK 0x0400
245#define INTR_EN0__INT_ACT 0x1000 245#define INTR_EN__UNSUP_CMD 0x0800
246#define INTR_EN0__RST_COMP 0x2000 246#define INTR_EN__INT_ACT 0x1000
247#define INTR_EN0__PIPE_CMD_ERR 0x4000 247#define INTR_EN__RST_COMP 0x2000
248#define INTR_EN0__PAGE_XFER_INC 0x8000 248#define INTR_EN__PIPE_CMD_ERR 0x4000
249 249#define INTR_EN__PAGE_XFER_INC 0x8000
250#define PAGE_CNT0 0x430 250
251#define PAGE_CNT0__VALUE 0x00ff 251#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
252 252#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
253#define ERR_PAGE_ADDR0 0x440 253#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
254#define ERR_PAGE_ADDR0__VALUE 0xffff
255
256#define ERR_BLOCK_ADDR0 0x450
257#define ERR_BLOCK_ADDR0__VALUE 0xffff
258
259#define INTR_STATUS1 0x460
260#define INTR_STATUS1__ECC_TRANSACTION_DONE 0x0001
261#define INTR_STATUS1__ECC_ERR 0x0002
262#define INTR_STATUS1__DMA_CMD_COMP 0x0004
263#define INTR_STATUS1__TIME_OUT 0x0008
264#define INTR_STATUS1__PROGRAM_FAIL 0x0010
265#define INTR_STATUS1__ERASE_FAIL 0x0020
266#define INTR_STATUS1__LOAD_COMP 0x0040
267#define INTR_STATUS1__PROGRAM_COMP 0x0080
268#define INTR_STATUS1__ERASE_COMP 0x0100
269#define INTR_STATUS1__PIPE_CPYBCK_CMD_COMP 0x0200
270#define INTR_STATUS1__LOCKED_BLK 0x0400
271#define INTR_STATUS1__UNSUP_CMD 0x0800
272#define INTR_STATUS1__INT_ACT 0x1000
273#define INTR_STATUS1__RST_COMP 0x2000
274#define INTR_STATUS1__PIPE_CMD_ERR 0x4000
275#define INTR_STATUS1__PAGE_XFER_INC 0x8000
276
277#define INTR_EN1 0x470
278#define INTR_EN1__ECC_TRANSACTION_DONE 0x0001
279#define INTR_EN1__ECC_ERR 0x0002
280#define INTR_EN1__DMA_CMD_COMP 0x0004
281#define INTR_EN1__TIME_OUT 0x0008
282#define INTR_EN1__PROGRAM_FAIL 0x0010
283#define INTR_EN1__ERASE_FAIL 0x0020
284#define INTR_EN1__LOAD_COMP 0x0040
285#define INTR_EN1__PROGRAM_COMP 0x0080
286#define INTR_EN1__ERASE_COMP 0x0100
287#define INTR_EN1__PIPE_CPYBCK_CMD_COMP 0x0200
288#define INTR_EN1__LOCKED_BLK 0x0400
289#define INTR_EN1__UNSUP_CMD 0x0800
290#define INTR_EN1__INT_ACT 0x1000
291#define INTR_EN1__RST_COMP 0x2000
292#define INTR_EN1__PIPE_CMD_ERR 0x4000
293#define INTR_EN1__PAGE_XFER_INC 0x8000
294
295#define PAGE_CNT1 0x480
296#define PAGE_CNT1__VALUE 0x00ff
297
298#define ERR_PAGE_ADDR1 0x490
299#define ERR_PAGE_ADDR1__VALUE 0xffff
300
301#define ERR_BLOCK_ADDR1 0x4a0
302#define ERR_BLOCK_ADDR1__VALUE 0xffff
303
304#define INTR_STATUS2 0x4b0
305#define INTR_STATUS2__ECC_TRANSACTION_DONE 0x0001
306#define INTR_STATUS2__ECC_ERR 0x0002
307#define INTR_STATUS2__DMA_CMD_COMP 0x0004
308#define INTR_STATUS2__TIME_OUT 0x0008
309#define INTR_STATUS2__PROGRAM_FAIL 0x0010
310#define INTR_STATUS2__ERASE_FAIL 0x0020
311#define INTR_STATUS2__LOAD_COMP 0x0040
312#define INTR_STATUS2__PROGRAM_COMP 0x0080
313#define INTR_STATUS2__ERASE_COMP 0x0100
314#define INTR_STATUS2__PIPE_CPYBCK_CMD_COMP 0x0200
315#define INTR_STATUS2__LOCKED_BLK 0x0400
316#define INTR_STATUS2__UNSUP_CMD 0x0800
317#define INTR_STATUS2__INT_ACT 0x1000
318#define INTR_STATUS2__RST_COMP 0x2000
319#define INTR_STATUS2__PIPE_CMD_ERR 0x4000
320#define INTR_STATUS2__PAGE_XFER_INC 0x8000
321
322#define INTR_EN2 0x4c0
323#define INTR_EN2__ECC_TRANSACTION_DONE 0x0001
324#define INTR_EN2__ECC_ERR 0x0002
325#define INTR_EN2__DMA_CMD_COMP 0x0004
326#define INTR_EN2__TIME_OUT 0x0008
327#define INTR_EN2__PROGRAM_FAIL 0x0010
328#define INTR_EN2__ERASE_FAIL 0x0020
329#define INTR_EN2__LOAD_COMP 0x0040
330#define INTR_EN2__PROGRAM_COMP 0x0080
331#define INTR_EN2__ERASE_COMP 0x0100
332#define INTR_EN2__PIPE_CPYBCK_CMD_COMP 0x0200
333#define INTR_EN2__LOCKED_BLK 0x0400
334#define INTR_EN2__UNSUP_CMD 0x0800
335#define INTR_EN2__INT_ACT 0x1000
336#define INTR_EN2__RST_COMP 0x2000
337#define INTR_EN2__PIPE_CMD_ERR 0x4000
338#define INTR_EN2__PAGE_XFER_INC 0x8000
339
340#define PAGE_CNT2 0x4d0
341#define PAGE_CNT2__VALUE 0x00ff
342
343#define ERR_PAGE_ADDR2 0x4e0
344#define ERR_PAGE_ADDR2__VALUE 0xffff
345
346#define ERR_BLOCK_ADDR2 0x4f0
347#define ERR_BLOCK_ADDR2__VALUE 0xffff
348
349#define INTR_STATUS3 0x500
350#define INTR_STATUS3__ECC_TRANSACTION_DONE 0x0001
351#define INTR_STATUS3__ECC_ERR 0x0002
352#define INTR_STATUS3__DMA_CMD_COMP 0x0004
353#define INTR_STATUS3__TIME_OUT 0x0008
354#define INTR_STATUS3__PROGRAM_FAIL 0x0010
355#define INTR_STATUS3__ERASE_FAIL 0x0020
356#define INTR_STATUS3__LOAD_COMP 0x0040
357#define INTR_STATUS3__PROGRAM_COMP 0x0080
358#define INTR_STATUS3__ERASE_COMP 0x0100
359#define INTR_STATUS3__PIPE_CPYBCK_CMD_COMP 0x0200
360#define INTR_STATUS3__LOCKED_BLK 0x0400
361#define INTR_STATUS3__UNSUP_CMD 0x0800
362#define INTR_STATUS3__INT_ACT 0x1000
363#define INTR_STATUS3__RST_COMP 0x2000
364#define INTR_STATUS3__PIPE_CMD_ERR 0x4000
365#define INTR_STATUS3__PAGE_XFER_INC 0x8000
366
367#define INTR_EN3 0x510
368#define INTR_EN3__ECC_TRANSACTION_DONE 0x0001
369#define INTR_EN3__ECC_ERR 0x0002
370#define INTR_EN3__DMA_CMD_COMP 0x0004
371#define INTR_EN3__TIME_OUT 0x0008
372#define INTR_EN3__PROGRAM_FAIL 0x0010
373#define INTR_EN3__ERASE_FAIL 0x0020
374#define INTR_EN3__LOAD_COMP 0x0040
375#define INTR_EN3__PROGRAM_COMP 0x0080
376#define INTR_EN3__ERASE_COMP 0x0100
377#define INTR_EN3__PIPE_CPYBCK_CMD_COMP 0x0200
378#define INTR_EN3__LOCKED_BLK 0x0400
379#define INTR_EN3__UNSUP_CMD 0x0800
380#define INTR_EN3__INT_ACT 0x1000
381#define INTR_EN3__RST_COMP 0x2000
382#define INTR_EN3__PIPE_CMD_ERR 0x4000
383#define INTR_EN3__PAGE_XFER_INC 0x8000
384
385#define PAGE_CNT3 0x520
386#define PAGE_CNT3__VALUE 0x00ff
387
388#define ERR_PAGE_ADDR3 0x530
389#define ERR_PAGE_ADDR3__VALUE 0xffff
390
391#define ERR_BLOCK_ADDR3 0x540
392#define ERR_BLOCK_ADDR3__VALUE 0xffff
393 254
394#define DATA_INTR 0x550 255#define DATA_INTR 0x550
395#define DATA_INTR__WRITE_SPACE_AV 0x0001 256#define DATA_INTR__WRITE_SPACE_AV 0x0001
@@ -484,141 +345,23 @@
484#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 345#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
485#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 346#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
486 347
487#define PERM_SRC_ID_0 0x830 348#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40))
488#define PERM_SRC_ID_0__SRCID 0x00ff 349#define PERM_SRC_ID__SRCID 0x00ff
489#define PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE 0x0800 350#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
490#define PERM_SRC_ID_0__WRITE_ACTIVE 0x2000 351#define PERM_SRC_ID__WRITE_ACTIVE 0x2000
491#define PERM_SRC_ID_0__READ_ACTIVE 0x4000 352#define PERM_SRC_ID__READ_ACTIVE 0x4000
492#define PERM_SRC_ID_0__PARTITION_VALID 0x8000 353#define PERM_SRC_ID__PARTITION_VALID 0x8000
493 354
494#define MIN_BLK_ADDR_0 0x840 355#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40))
495#define MIN_BLK_ADDR_0__VALUE 0xffff 356#define MIN_BLK_ADDR__VALUE 0xffff
496 357
497#define MAX_BLK_ADDR_0 0x850 358#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40))
498#define MAX_BLK_ADDR_0__VALUE 0xffff 359#define MAX_BLK_ADDR__VALUE 0xffff
499 360
500#define MIN_MAX_BANK_0 0x860 361#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40))
501#define MIN_MAX_BANK_0__MIN_VALUE 0x0003 362#define MIN_MAX_BANK__MIN_VALUE 0x0003
502#define MIN_MAX_BANK_0__MAX_VALUE 0x000c 363#define MIN_MAX_BANK__MAX_VALUE 0x000c
503 364
504#define PERM_SRC_ID_1 0x870
505#define PERM_SRC_ID_1__SRCID 0x00ff
506#define PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE 0x0800
507#define PERM_SRC_ID_1__WRITE_ACTIVE 0x2000
508#define PERM_SRC_ID_1__READ_ACTIVE 0x4000
509#define PERM_SRC_ID_1__PARTITION_VALID 0x8000
510
511#define MIN_BLK_ADDR_1 0x880
512#define MIN_BLK_ADDR_1__VALUE 0xffff
513
514#define MAX_BLK_ADDR_1 0x890
515#define MAX_BLK_ADDR_1__VALUE 0xffff
516
517#define MIN_MAX_BANK_1 0x8a0
518#define MIN_MAX_BANK_1__MIN_VALUE 0x0003
519#define MIN_MAX_BANK_1__MAX_VALUE 0x000c
520
521#define PERM_SRC_ID_2 0x8b0
522#define PERM_SRC_ID_2__SRCID 0x00ff
523#define PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE 0x0800
524#define PERM_SRC_ID_2__WRITE_ACTIVE 0x2000
525#define PERM_SRC_ID_2__READ_ACTIVE 0x4000
526#define PERM_SRC_ID_2__PARTITION_VALID 0x8000
527
528#define MIN_BLK_ADDR_2 0x8c0
529#define MIN_BLK_ADDR_2__VALUE 0xffff
530
531#define MAX_BLK_ADDR_2 0x8d0
532#define MAX_BLK_ADDR_2__VALUE 0xffff
533
534#define MIN_MAX_BANK_2 0x8e0
535#define MIN_MAX_BANK_2__MIN_VALUE 0x0003
536#define MIN_MAX_BANK_2__MAX_VALUE 0x000c
537
538#define PERM_SRC_ID_3 0x8f0
539#define PERM_SRC_ID_3__SRCID 0x00ff
540#define PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE 0x0800
541#define PERM_SRC_ID_3__WRITE_ACTIVE 0x2000
542#define PERM_SRC_ID_3__READ_ACTIVE 0x4000
543#define PERM_SRC_ID_3__PARTITION_VALID 0x8000
544
545#define MIN_BLK_ADDR_3 0x900
546#define MIN_BLK_ADDR_3__VALUE 0xffff
547
548#define MAX_BLK_ADDR_3 0x910
549#define MAX_BLK_ADDR_3__VALUE 0xffff
550
551#define MIN_MAX_BANK_3 0x920
552#define MIN_MAX_BANK_3__MIN_VALUE 0x0003
553#define MIN_MAX_BANK_3__MAX_VALUE 0x000c
554
555#define PERM_SRC_ID_4 0x930
556#define PERM_SRC_ID_4__SRCID 0x00ff
557#define PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE 0x0800
558#define PERM_SRC_ID_4__WRITE_ACTIVE 0x2000
559#define PERM_SRC_ID_4__READ_ACTIVE 0x4000
560#define PERM_SRC_ID_4__PARTITION_VALID 0x8000
561
562#define MIN_BLK_ADDR_4 0x940
563#define MIN_BLK_ADDR_4__VALUE 0xffff
564
565#define MAX_BLK_ADDR_4 0x950
566#define MAX_BLK_ADDR_4__VALUE 0xffff
567
568#define MIN_MAX_BANK_4 0x960
569#define MIN_MAX_BANK_4__MIN_VALUE 0x0003
570#define MIN_MAX_BANK_4__MAX_VALUE 0x000c
571
572#define PERM_SRC_ID_5 0x970
573#define PERM_SRC_ID_5__SRCID 0x00ff
574#define PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE 0x0800
575#define PERM_SRC_ID_5__WRITE_ACTIVE 0x2000
576#define PERM_SRC_ID_5__READ_ACTIVE 0x4000
577#define PERM_SRC_ID_5__PARTITION_VALID 0x8000
578
579#define MIN_BLK_ADDR_5 0x980
580#define MIN_BLK_ADDR_5__VALUE 0xffff
581
582#define MAX_BLK_ADDR_5 0x990
583#define MAX_BLK_ADDR_5__VALUE 0xffff
584
585#define MIN_MAX_BANK_5 0x9a0
586#define MIN_MAX_BANK_5__MIN_VALUE 0x0003
587#define MIN_MAX_BANK_5__MAX_VALUE 0x000c
588
589#define PERM_SRC_ID_6 0x9b0
590#define PERM_SRC_ID_6__SRCID 0x00ff
591#define PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE 0x0800
592#define PERM_SRC_ID_6__WRITE_ACTIVE 0x2000
593#define PERM_SRC_ID_6__READ_ACTIVE 0x4000
594#define PERM_SRC_ID_6__PARTITION_VALID 0x8000
595
596#define MIN_BLK_ADDR_6 0x9c0
597#define MIN_BLK_ADDR_6__VALUE 0xffff
598
599#define MAX_BLK_ADDR_6 0x9d0
600#define MAX_BLK_ADDR_6__VALUE 0xffff
601
602#define MIN_MAX_BANK_6 0x9e0
603#define MIN_MAX_BANK_6__MIN_VALUE 0x0003
604#define MIN_MAX_BANK_6__MAX_VALUE 0x000c
605
606#define PERM_SRC_ID_7 0x9f0
607#define PERM_SRC_ID_7__SRCID 0x00ff
608#define PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE 0x0800
609#define PERM_SRC_ID_7__WRITE_ACTIVE 0x2000
610#define PERM_SRC_ID_7__READ_ACTIVE 0x4000
611#define PERM_SRC_ID_7__PARTITION_VALID 0x8000
612
613#define MIN_BLK_ADDR_7 0xa00
614#define MIN_BLK_ADDR_7__VALUE 0xffff
615
616#define MAX_BLK_ADDR_7 0xa10
617#define MAX_BLK_ADDR_7__VALUE 0xffff
618
619#define MIN_MAX_BANK_7 0xa20
620#define MIN_MAX_BANK_7__MIN_VALUE 0x0003
621#define MIN_MAX_BANK_7__MAX_VALUE 0x000c
622 365
623/* ffsdefs.h */ 366/* ffsdefs.h */
624#define CLEAR 0 /*use this to clear a field instead of "fail"*/ 367#define CLEAR 0 /*use this to clear a field instead of "fail"*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 00:21:20 -0500