diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-11-22 17:56:30 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-11-22 18:23:27 -0500 |
commit | 958261d1e8755d1423beb0951ed0b9552c96f638 (patch) | |
tree | 558915a5c1f76165474ea768635257d3e1d5ab2c | |
parent | 180074010c6a8d1948638b4a136d2bd8111f4459 (diff) |
drm/radeon/kms: add radeon_asic struct for AMD Ontario fusion APUs
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index bf7ec0441e63..4e487cc16e7f 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -751,6 +751,49 @@ static struct radeon_asic evergreen_asic = { | |||
751 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | 751 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
752 | }; | 752 | }; |
753 | 753 | ||
754 | static struct radeon_asic sumo_asic = { | ||
755 | .init = &evergreen_init, | ||
756 | .fini = &evergreen_fini, | ||
757 | .suspend = &evergreen_suspend, | ||
758 | .resume = &evergreen_resume, | ||
759 | .cp_commit = &r600_cp_commit, | ||
760 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | ||
761 | .asic_reset = &evergreen_asic_reset, | ||
762 | .vga_set_state = &r600_vga_set_state, | ||
763 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | ||
764 | .gart_set_page = &rs600_gart_set_page, | ||
765 | .ring_test = &r600_ring_test, | ||
766 | .ring_ib_execute = &r600_ring_ib_execute, | ||
767 | .irq_set = &evergreen_irq_set, | ||
768 | .irq_process = &evergreen_irq_process, | ||
769 | .get_vblank_counter = &evergreen_get_vblank_counter, | ||
770 | .fence_ring_emit = &r600_fence_ring_emit, | ||
771 | .cs_parse = &evergreen_cs_parse, | ||
772 | .copy_blit = NULL, | ||
773 | .copy_dma = NULL, | ||
774 | .copy = NULL, | ||
775 | .get_engine_clock = &radeon_atom_get_engine_clock, | ||
776 | .set_engine_clock = &radeon_atom_set_engine_clock, | ||
777 | .get_memory_clock = NULL, | ||
778 | .set_memory_clock = NULL, | ||
779 | .get_pcie_lanes = NULL, | ||
780 | .set_pcie_lanes = NULL, | ||
781 | .set_clock_gating = NULL, | ||
782 | .set_surface_reg = r600_set_surface_reg, | ||
783 | .clear_surface_reg = r600_clear_surface_reg, | ||
784 | .bandwidth_update = &evergreen_bandwidth_update, | ||
785 | .hpd_init = &evergreen_hpd_init, | ||
786 | .hpd_fini = &evergreen_hpd_fini, | ||
787 | .hpd_sense = &evergreen_hpd_sense, | ||
788 | .hpd_set_polarity = &evergreen_hpd_set_polarity, | ||
789 | .gui_idle = &r600_gui_idle, | ||
790 | .pm_misc = &evergreen_pm_misc, | ||
791 | .pm_prepare = &evergreen_pm_prepare, | ||
792 | .pm_finish = &evergreen_pm_finish, | ||
793 | .pm_init_profile = &rs780_pm_init_profile, | ||
794 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | ||
795 | }; | ||
796 | |||
754 | int radeon_asic_init(struct radeon_device *rdev) | 797 | int radeon_asic_init(struct radeon_device *rdev) |
755 | { | 798 | { |
756 | radeon_register_accessor_init(rdev); | 799 | radeon_register_accessor_init(rdev); |
@@ -835,6 +878,9 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
835 | case CHIP_HEMLOCK: | 878 | case CHIP_HEMLOCK: |
836 | rdev->asic = &evergreen_asic; | 879 | rdev->asic = &evergreen_asic; |
837 | break; | 880 | break; |
881 | case CHIP_PALM: | ||
882 | rdev->asic = &sumo_asic; | ||
883 | break; | ||
838 | default: | 884 | default: |
839 | /* FIXME: not supported yet */ | 885 | /* FIXME: not supported yet */ |
840 | return -EINVAL; | 886 | return -EINVAL; |