diff options
author | Joe Perches <joe@perches.com> | 2013-04-09 06:18:14 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2013-04-09 17:07:52 -0400 |
commit | 953c96e0d85615d1ab1f100e525d376053294dc2 (patch) | |
tree | a2503a75ee16884c1373d591a4618ef45ecfa911 | |
parent | 712c4b7439be77b7a0d8d0c1139a0ef1c52565aa (diff) |
tg3: Use bool not int
Using bool can make code more readable.
Convert uses and tests of int to bool.
This also makes a comparison of tg3->link_up
(itself bool) a bool comparison instead of int.
Reorder stack variable declarations to make
bool fit declaration holes where appropriate.
$ size drivers/net/ethernet/broadcom/tg3.o*
text data bss dec hex filename
169958 27249 58896 256103 3e867 drivers/net/ethernet/broadcom/tg3.o.new
169968 27249 58896 256113 3e871 drivers/net/ethernet/broadcom/tg3.o.old
Signed-off-by: Joe Perches <joe@perches.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 157 |
1 files changed, 80 insertions, 77 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 0fe64442903f..ce985729f3e6 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c | |||
@@ -2228,7 +2228,7 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | |||
2228 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | 2228 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); |
2229 | } | 2229 | } |
2230 | 2230 | ||
2231 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) | 2231 | static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) |
2232 | { | 2232 | { |
2233 | u32 phy; | 2233 | u32 phy; |
2234 | 2234 | ||
@@ -2320,7 +2320,7 @@ static void tg3_phy_apply_otp(struct tg3 *tp) | |||
2320 | tg3_phy_toggle_auxctl_smdsp(tp, false); | 2320 | tg3_phy_toggle_auxctl_smdsp(tp, false); |
2321 | } | 2321 | } |
2322 | 2322 | ||
2323 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) | 2323 | static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) |
2324 | { | 2324 | { |
2325 | u32 val; | 2325 | u32 val; |
2326 | 2326 | ||
@@ -2330,7 +2330,7 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) | |||
2330 | tp->setlpicnt = 0; | 2330 | tp->setlpicnt = 0; |
2331 | 2331 | ||
2332 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | 2332 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
2333 | current_link_up == 1 && | 2333 | current_link_up && |
2334 | tp->link_config.active_duplex == DUPLEX_FULL && | 2334 | tp->link_config.active_duplex == DUPLEX_FULL && |
2335 | (tp->link_config.active_speed == SPEED_100 || | 2335 | (tp->link_config.active_speed == SPEED_100 || |
2336 | tp->link_config.active_speed == SPEED_1000)) { | 2336 | tp->link_config.active_speed == SPEED_1000)) { |
@@ -2352,7 +2352,7 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) | |||
2352 | } | 2352 | } |
2353 | 2353 | ||
2354 | if (!tp->setlpicnt) { | 2354 | if (!tp->setlpicnt) { |
2355 | if (current_link_up == 1 && | 2355 | if (current_link_up && |
2356 | !tg3_phy_toggle_auxctl_smdsp(tp, true)) { | 2356 | !tg3_phy_toggle_auxctl_smdsp(tp, true)) { |
2357 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | 2357 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); |
2358 | tg3_phy_toggle_auxctl_smdsp(tp, false); | 2358 | tg3_phy_toggle_auxctl_smdsp(tp, false); |
@@ -2705,7 +2705,7 @@ out: | |||
2705 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) | 2705 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) |
2706 | tg3_phydsp_write(tp, 0xffb, 0x4000); | 2706 | tg3_phydsp_write(tp, 0xffb, 0x4000); |
2707 | 2707 | ||
2708 | tg3_phy_toggle_automdix(tp, 1); | 2708 | tg3_phy_toggle_automdix(tp, true); |
2709 | tg3_phy_set_wirespeed(tp); | 2709 | tg3_phy_set_wirespeed(tp); |
2710 | return 0; | 2710 | return 0; |
2711 | } | 2711 | } |
@@ -3851,7 +3851,7 @@ static int tg3_load_tso_firmware(struct tg3 *tp) | |||
3851 | 3851 | ||
3852 | 3852 | ||
3853 | /* tp->lock is held. */ | 3853 | /* tp->lock is held. */ |
3854 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | 3854 | static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) |
3855 | { | 3855 | { |
3856 | u32 addr_high, addr_low; | 3856 | u32 addr_high, addr_low; |
3857 | int i; | 3857 | int i; |
@@ -3914,7 +3914,7 @@ static int tg3_power_up(struct tg3 *tp) | |||
3914 | return err; | 3914 | return err; |
3915 | } | 3915 | } |
3916 | 3916 | ||
3917 | static int tg3_setup_phy(struct tg3 *, int); | 3917 | static int tg3_setup_phy(struct tg3 *, bool); |
3918 | 3918 | ||
3919 | static int tg3_power_down_prepare(struct tg3 *tp) | 3919 | static int tg3_power_down_prepare(struct tg3 *tp) |
3920 | { | 3920 | { |
@@ -3986,7 +3986,7 @@ static int tg3_power_down_prepare(struct tg3 *tp) | |||
3986 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | 3986 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
3987 | 3987 | ||
3988 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | 3988 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
3989 | tg3_setup_phy(tp, 0); | 3989 | tg3_setup_phy(tp, false); |
3990 | } | 3990 | } |
3991 | 3991 | ||
3992 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { | 3992 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
@@ -4583,7 +4583,7 @@ static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) | |||
4583 | return true; | 4583 | return true; |
4584 | } | 4584 | } |
4585 | 4585 | ||
4586 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up) | 4586 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) |
4587 | { | 4587 | { |
4588 | if (curr_link_up != tp->link_up) { | 4588 | if (curr_link_up != tp->link_up) { |
4589 | if (curr_link_up) { | 4589 | if (curr_link_up) { |
@@ -4613,9 +4613,9 @@ static void tg3_clear_mac_status(struct tg3 *tp) | |||
4613 | udelay(40); | 4613 | udelay(40); |
4614 | } | 4614 | } |
4615 | 4615 | ||
4616 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | 4616 | static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) |
4617 | { | 4617 | { |
4618 | int current_link_up; | 4618 | bool current_link_up; |
4619 | u32 bmsr, val; | 4619 | u32 bmsr, val; |
4620 | u32 lcl_adv, rmt_adv; | 4620 | u32 lcl_adv, rmt_adv; |
4621 | u16 current_speed; | 4621 | u16 current_speed; |
@@ -4642,7 +4642,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4642 | tg3_readphy(tp, MII_BMSR, &bmsr); | 4642 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4643 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | 4643 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
4644 | !(bmsr & BMSR_LSTATUS)) | 4644 | !(bmsr & BMSR_LSTATUS)) |
4645 | force_reset = 1; | 4645 | force_reset = true; |
4646 | } | 4646 | } |
4647 | if (force_reset) | 4647 | if (force_reset) |
4648 | tg3_phy_reset(tp); | 4648 | tg3_phy_reset(tp); |
@@ -4706,7 +4706,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4706 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | 4706 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); |
4707 | } | 4707 | } |
4708 | 4708 | ||
4709 | current_link_up = 0; | 4709 | current_link_up = false; |
4710 | current_speed = SPEED_UNKNOWN; | 4710 | current_speed = SPEED_UNKNOWN; |
4711 | current_duplex = DUPLEX_UNKNOWN; | 4711 | current_duplex = DUPLEX_UNKNOWN; |
4712 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; | 4712 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; |
@@ -4771,7 +4771,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4771 | eee_config_ok && | 4771 | eee_config_ok && |
4772 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && | 4772 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && |
4773 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) | 4773 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) |
4774 | current_link_up = 1; | 4774 | current_link_up = true; |
4775 | 4775 | ||
4776 | /* EEE settings changes take effect only after a phy | 4776 | /* EEE settings changes take effect only after a phy |
4777 | * reset. If we have skipped a reset due to Link Flap | 4777 | * reset. If we have skipped a reset due to Link Flap |
@@ -4785,11 +4785,11 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4785 | if (!(bmcr & BMCR_ANENABLE) && | 4785 | if (!(bmcr & BMCR_ANENABLE) && |
4786 | tp->link_config.speed == current_speed && | 4786 | tp->link_config.speed == current_speed && |
4787 | tp->link_config.duplex == current_duplex) { | 4787 | tp->link_config.duplex == current_duplex) { |
4788 | current_link_up = 1; | 4788 | current_link_up = true; |
4789 | } | 4789 | } |
4790 | } | 4790 | } |
4791 | 4791 | ||
4792 | if (current_link_up == 1 && | 4792 | if (current_link_up && |
4793 | tp->link_config.active_duplex == DUPLEX_FULL) { | 4793 | tp->link_config.active_duplex == DUPLEX_FULL) { |
4794 | u32 reg, bit; | 4794 | u32 reg, bit; |
4795 | 4795 | ||
@@ -4809,11 +4809,11 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4809 | } | 4809 | } |
4810 | 4810 | ||
4811 | relink: | 4811 | relink: |
4812 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | 4812 | if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
4813 | tg3_phy_copper_begin(tp); | 4813 | tg3_phy_copper_begin(tp); |
4814 | 4814 | ||
4815 | if (tg3_flag(tp, ROBOSWITCH)) { | 4815 | if (tg3_flag(tp, ROBOSWITCH)) { |
4816 | current_link_up = 1; | 4816 | current_link_up = true; |
4817 | /* FIXME: when BCM5325 switch is used use 100 MBit/s */ | 4817 | /* FIXME: when BCM5325 switch is used use 100 MBit/s */ |
4818 | current_speed = SPEED_1000; | 4818 | current_speed = SPEED_1000; |
4819 | current_duplex = DUPLEX_FULL; | 4819 | current_duplex = DUPLEX_FULL; |
@@ -4824,11 +4824,11 @@ relink: | |||
4824 | tg3_readphy(tp, MII_BMSR, &bmsr); | 4824 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4825 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || | 4825 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
4826 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | 4826 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) |
4827 | current_link_up = 1; | 4827 | current_link_up = true; |
4828 | } | 4828 | } |
4829 | 4829 | ||
4830 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | 4830 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; |
4831 | if (current_link_up == 1) { | 4831 | if (current_link_up) { |
4832 | if (tp->link_config.active_speed == SPEED_100 || | 4832 | if (tp->link_config.active_speed == SPEED_100 || |
4833 | tp->link_config.active_speed == SPEED_10) | 4833 | tp->link_config.active_speed == SPEED_10) |
4834 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | 4834 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
@@ -4864,7 +4864,7 @@ relink: | |||
4864 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | 4864 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; |
4865 | 4865 | ||
4866 | if (tg3_asic_rev(tp) == ASIC_REV_5700) { | 4866 | if (tg3_asic_rev(tp) == ASIC_REV_5700) { |
4867 | if (current_link_up == 1 && | 4867 | if (current_link_up && |
4868 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | 4868 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) |
4869 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | 4869 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
4870 | else | 4870 | else |
@@ -4895,7 +4895,7 @@ relink: | |||
4895 | udelay(40); | 4895 | udelay(40); |
4896 | 4896 | ||
4897 | if (tg3_asic_rev(tp) == ASIC_REV_5700 && | 4897 | if (tg3_asic_rev(tp) == ASIC_REV_5700 && |
4898 | current_link_up == 1 && | 4898 | current_link_up && |
4899 | tp->link_config.active_speed == SPEED_1000 && | 4899 | tp->link_config.active_speed == SPEED_1000 && |
4900 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { | 4900 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
4901 | udelay(120); | 4901 | udelay(120); |
@@ -5335,19 +5335,19 @@ static void tg3_init_bcm8002(struct tg3 *tp) | |||
5335 | tg3_writephy(tp, 0x10, 0x8011); | 5335 | tg3_writephy(tp, 0x10, 0x8011); |
5336 | } | 5336 | } |
5337 | 5337 | ||
5338 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | 5338 | static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) |
5339 | { | 5339 | { |
5340 | u16 flowctrl; | 5340 | u16 flowctrl; |
5341 | bool current_link_up; | ||
5341 | u32 sg_dig_ctrl, sg_dig_status; | 5342 | u32 sg_dig_ctrl, sg_dig_status; |
5342 | u32 serdes_cfg, expected_sg_dig_ctrl; | 5343 | u32 serdes_cfg, expected_sg_dig_ctrl; |
5343 | int workaround, port_a; | 5344 | int workaround, port_a; |
5344 | int current_link_up; | ||
5345 | 5345 | ||
5346 | serdes_cfg = 0; | 5346 | serdes_cfg = 0; |
5347 | expected_sg_dig_ctrl = 0; | 5347 | expected_sg_dig_ctrl = 0; |
5348 | workaround = 0; | 5348 | workaround = 0; |
5349 | port_a = 1; | 5349 | port_a = 1; |
5350 | current_link_up = 0; | 5350 | current_link_up = false; |
5351 | 5351 | ||
5352 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && | 5352 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && |
5353 | tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { | 5353 | tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { |
@@ -5378,7 +5378,7 @@ static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |||
5378 | } | 5378 | } |
5379 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | 5379 | if (mac_status & MAC_STATUS_PCS_SYNCED) { |
5380 | tg3_setup_flow_control(tp, 0, 0); | 5380 | tg3_setup_flow_control(tp, 0, 0); |
5381 | current_link_up = 1; | 5381 | current_link_up = true; |
5382 | } | 5382 | } |
5383 | goto out; | 5383 | goto out; |
5384 | } | 5384 | } |
@@ -5399,7 +5399,7 @@ static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |||
5399 | MAC_STATUS_RCVD_CFG)) == | 5399 | MAC_STATUS_RCVD_CFG)) == |
5400 | MAC_STATUS_PCS_SYNCED)) { | 5400 | MAC_STATUS_PCS_SYNCED)) { |
5401 | tp->serdes_counter--; | 5401 | tp->serdes_counter--; |
5402 | current_link_up = 1; | 5402 | current_link_up = true; |
5403 | goto out; | 5403 | goto out; |
5404 | } | 5404 | } |
5405 | restart_autoneg: | 5405 | restart_autoneg: |
@@ -5434,7 +5434,7 @@ restart_autoneg: | |||
5434 | mii_adv_to_ethtool_adv_x(remote_adv); | 5434 | mii_adv_to_ethtool_adv_x(remote_adv); |
5435 | 5435 | ||
5436 | tg3_setup_flow_control(tp, local_adv, remote_adv); | 5436 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
5437 | current_link_up = 1; | 5437 | current_link_up = true; |
5438 | tp->serdes_counter = 0; | 5438 | tp->serdes_counter = 0; |
5439 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | 5439 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
5440 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { | 5440 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
@@ -5462,7 +5462,7 @@ restart_autoneg: | |||
5462 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | 5462 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && |
5463 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | 5463 | !(mac_status & MAC_STATUS_RCVD_CFG)) { |
5464 | tg3_setup_flow_control(tp, 0, 0); | 5464 | tg3_setup_flow_control(tp, 0, 0); |
5465 | current_link_up = 1; | 5465 | current_link_up = true; |
5466 | tp->phy_flags |= | 5466 | tp->phy_flags |= |
5467 | TG3_PHYFLG_PARALLEL_DETECT; | 5467 | TG3_PHYFLG_PARALLEL_DETECT; |
5468 | tp->serdes_counter = | 5468 | tp->serdes_counter = |
@@ -5480,9 +5480,9 @@ out: | |||
5480 | return current_link_up; | 5480 | return current_link_up; |
5481 | } | 5481 | } |
5482 | 5482 | ||
5483 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | 5483 | static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) |
5484 | { | 5484 | { |
5485 | int current_link_up = 0; | 5485 | bool current_link_up = false; |
5486 | 5486 | ||
5487 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) | 5487 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
5488 | goto out; | 5488 | goto out; |
@@ -5509,7 +5509,7 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |||
5509 | 5509 | ||
5510 | tg3_setup_flow_control(tp, local_adv, remote_adv); | 5510 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
5511 | 5511 | ||
5512 | current_link_up = 1; | 5512 | current_link_up = true; |
5513 | } | 5513 | } |
5514 | for (i = 0; i < 30; i++) { | 5514 | for (i = 0; i < 30; i++) { |
5515 | udelay(20); | 5515 | udelay(20); |
@@ -5524,15 +5524,15 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |||
5524 | } | 5524 | } |
5525 | 5525 | ||
5526 | mac_status = tr32(MAC_STATUS); | 5526 | mac_status = tr32(MAC_STATUS); |
5527 | if (current_link_up == 0 && | 5527 | if (!current_link_up && |
5528 | (mac_status & MAC_STATUS_PCS_SYNCED) && | 5528 | (mac_status & MAC_STATUS_PCS_SYNCED) && |
5529 | !(mac_status & MAC_STATUS_RCVD_CFG)) | 5529 | !(mac_status & MAC_STATUS_RCVD_CFG)) |
5530 | current_link_up = 1; | 5530 | current_link_up = true; |
5531 | } else { | 5531 | } else { |
5532 | tg3_setup_flow_control(tp, 0, 0); | 5532 | tg3_setup_flow_control(tp, 0, 0); |
5533 | 5533 | ||
5534 | /* Forcing 1000FD link up. */ | 5534 | /* Forcing 1000FD link up. */ |
5535 | current_link_up = 1; | 5535 | current_link_up = true; |
5536 | 5536 | ||
5537 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | 5537 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); |
5538 | udelay(40); | 5538 | udelay(40); |
@@ -5545,13 +5545,13 @@ out: | |||
5545 | return current_link_up; | 5545 | return current_link_up; |
5546 | } | 5546 | } |
5547 | 5547 | ||
5548 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | 5548 | static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) |
5549 | { | 5549 | { |
5550 | u32 orig_pause_cfg; | 5550 | u32 orig_pause_cfg; |
5551 | u16 orig_active_speed; | 5551 | u16 orig_active_speed; |
5552 | u8 orig_active_duplex; | 5552 | u8 orig_active_duplex; |
5553 | u32 mac_status; | 5553 | u32 mac_status; |
5554 | int current_link_up; | 5554 | bool current_link_up; |
5555 | int i; | 5555 | int i; |
5556 | 5556 | ||
5557 | orig_pause_cfg = tp->link_config.active_flowctrl; | 5557 | orig_pause_cfg = tp->link_config.active_flowctrl; |
@@ -5588,7 +5588,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |||
5588 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | 5588 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); |
5589 | udelay(40); | 5589 | udelay(40); |
5590 | 5590 | ||
5591 | current_link_up = 0; | 5591 | current_link_up = false; |
5592 | tp->link_config.rmt_adv = 0; | 5592 | tp->link_config.rmt_adv = 0; |
5593 | mac_status = tr32(MAC_STATUS); | 5593 | mac_status = tr32(MAC_STATUS); |
5594 | 5594 | ||
@@ -5613,7 +5613,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |||
5613 | 5613 | ||
5614 | mac_status = tr32(MAC_STATUS); | 5614 | mac_status = tr32(MAC_STATUS); |
5615 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | 5615 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { |
5616 | current_link_up = 0; | 5616 | current_link_up = false; |
5617 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | 5617 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
5618 | tp->serdes_counter == 0) { | 5618 | tp->serdes_counter == 0) { |
5619 | tw32_f(MAC_MODE, (tp->mac_mode | | 5619 | tw32_f(MAC_MODE, (tp->mac_mode | |
@@ -5623,7 +5623,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |||
5623 | } | 5623 | } |
5624 | } | 5624 | } |
5625 | 5625 | ||
5626 | if (current_link_up == 1) { | 5626 | if (current_link_up) { |
5627 | tp->link_config.active_speed = SPEED_1000; | 5627 | tp->link_config.active_speed = SPEED_1000; |
5628 | tp->link_config.active_duplex = DUPLEX_FULL; | 5628 | tp->link_config.active_duplex = DUPLEX_FULL; |
5629 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | 5629 | tw32(MAC_LED_CTRL, (tp->led_ctrl | |
@@ -5648,12 +5648,13 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |||
5648 | return 0; | 5648 | return 0; |
5649 | } | 5649 | } |
5650 | 5650 | ||
5651 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | 5651 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) |
5652 | { | 5652 | { |
5653 | int current_link_up = 0, err = 0; | 5653 | int err = 0; |
5654 | u32 bmsr, bmcr; | 5654 | u32 bmsr, bmcr; |
5655 | u16 current_speed = SPEED_UNKNOWN; | 5655 | u16 current_speed = SPEED_UNKNOWN; |
5656 | u8 current_duplex = DUPLEX_UNKNOWN; | 5656 | u8 current_duplex = DUPLEX_UNKNOWN; |
5657 | bool current_link_up = false; | ||
5657 | u32 local_adv, remote_adv, sgsr; | 5658 | u32 local_adv, remote_adv, sgsr; |
5658 | 5659 | ||
5659 | if ((tg3_asic_rev(tp) == ASIC_REV_5719 || | 5660 | if ((tg3_asic_rev(tp) == ASIC_REV_5719 || |
@@ -5669,7 +5670,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |||
5669 | if (!(sgsr & SERDES_TG3_LINK_UP)) { | 5670 | if (!(sgsr & SERDES_TG3_LINK_UP)) { |
5670 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | 5671 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
5671 | } else { | 5672 | } else { |
5672 | current_link_up = 1; | 5673 | current_link_up = true; |
5673 | if (sgsr & SERDES_TG3_SPEED_1000) { | 5674 | if (sgsr & SERDES_TG3_SPEED_1000) { |
5674 | current_speed = SPEED_1000; | 5675 | current_speed = SPEED_1000; |
5675 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | 5676 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
@@ -5789,7 +5790,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |||
5789 | 5790 | ||
5790 | if (bmsr & BMSR_LSTATUS) { | 5791 | if (bmsr & BMSR_LSTATUS) { |
5791 | current_speed = SPEED_1000; | 5792 | current_speed = SPEED_1000; |
5792 | current_link_up = 1; | 5793 | current_link_up = true; |
5793 | if (bmcr & BMCR_FULLDPLX) | 5794 | if (bmcr & BMCR_FULLDPLX) |
5794 | current_duplex = DUPLEX_FULL; | 5795 | current_duplex = DUPLEX_FULL; |
5795 | else | 5796 | else |
@@ -5816,13 +5817,13 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |||
5816 | } else if (!tg3_flag(tp, 5780_CLASS)) { | 5817 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
5817 | /* Link is up via parallel detect */ | 5818 | /* Link is up via parallel detect */ |
5818 | } else { | 5819 | } else { |
5819 | current_link_up = 0; | 5820 | current_link_up = false; |
5820 | } | 5821 | } |
5821 | } | 5822 | } |
5822 | } | 5823 | } |
5823 | 5824 | ||
5824 | fiber_setup_done: | 5825 | fiber_setup_done: |
5825 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) | 5826 | if (current_link_up && current_duplex == DUPLEX_FULL) |
5826 | tg3_setup_flow_control(tp, local_adv, remote_adv); | 5827 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
5827 | 5828 | ||
5828 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | 5829 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
@@ -5901,7 +5902,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp) | |||
5901 | } | 5902 | } |
5902 | } | 5903 | } |
5903 | 5904 | ||
5904 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) | 5905 | static int tg3_setup_phy(struct tg3 *tp, bool force_reset) |
5905 | { | 5906 | { |
5906 | u32 val; | 5907 | u32 val; |
5907 | int err; | 5908 | int err; |
@@ -6802,7 +6803,7 @@ static void tg3_poll_link(struct tg3 *tp) | |||
6802 | MAC_STATUS_LNKSTATE_CHANGED)); | 6803 | MAC_STATUS_LNKSTATE_CHANGED)); |
6803 | udelay(40); | 6804 | udelay(40); |
6804 | } else | 6805 | } else |
6805 | tg3_setup_phy(tp, 0); | 6806 | tg3_setup_phy(tp, false); |
6806 | spin_unlock(&tp->lock); | 6807 | spin_unlock(&tp->lock); |
6807 | } | 6808 | } |
6808 | } | 6809 | } |
@@ -7899,7 +7900,7 @@ static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) | |||
7899 | u32 val, bmcr, mac_mode, ptest = 0; | 7900 | u32 val, bmcr, mac_mode, ptest = 0; |
7900 | 7901 | ||
7901 | tg3_phy_toggle_apd(tp, false); | 7902 | tg3_phy_toggle_apd(tp, false); |
7902 | tg3_phy_toggle_automdix(tp, 0); | 7903 | tg3_phy_toggle_automdix(tp, false); |
7903 | 7904 | ||
7904 | if (extlpbk && tg3_phy_set_extloopbk(tp)) | 7905 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
7905 | return -EIO; | 7906 | return -EIO; |
@@ -8007,7 +8008,7 @@ static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) | |||
8007 | spin_lock_bh(&tp->lock); | 8008 | spin_lock_bh(&tp->lock); |
8008 | tg3_mac_loopback(tp, false); | 8009 | tg3_mac_loopback(tp, false); |
8009 | /* Force link status check */ | 8010 | /* Force link status check */ |
8010 | tg3_setup_phy(tp, 1); | 8011 | tg3_setup_phy(tp, true); |
8011 | spin_unlock_bh(&tp->lock); | 8012 | spin_unlock_bh(&tp->lock); |
8012 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | 8013 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); |
8013 | } | 8014 | } |
@@ -8518,7 +8519,7 @@ err_out: | |||
8518 | /* To stop a block, clear the enable bit and poll till it | 8519 | /* To stop a block, clear the enable bit and poll till it |
8519 | * clears. tp->lock is held. | 8520 | * clears. tp->lock is held. |
8520 | */ | 8521 | */ |
8521 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) | 8522 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) |
8522 | { | 8523 | { |
8523 | unsigned int i; | 8524 | unsigned int i; |
8524 | u32 val; | 8525 | u32 val; |
@@ -8562,7 +8563,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int | |||
8562 | } | 8563 | } |
8563 | 8564 | ||
8564 | /* tp->lock is held. */ | 8565 | /* tp->lock is held. */ |
8565 | static int tg3_abort_hw(struct tg3 *tp, int silent) | 8566 | static int tg3_abort_hw(struct tg3 *tp, bool silent) |
8566 | { | 8567 | { |
8567 | int i, err; | 8568 | int i, err; |
8568 | 8569 | ||
@@ -8952,7 +8953,7 @@ static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *); | |||
8952 | static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); | 8953 | static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); |
8953 | 8954 | ||
8954 | /* tp->lock is held. */ | 8955 | /* tp->lock is held. */ |
8955 | static int tg3_halt(struct tg3 *tp, int kind, int silent) | 8956 | static int tg3_halt(struct tg3 *tp, int kind, bool silent) |
8956 | { | 8957 | { |
8957 | int err; | 8958 | int err; |
8958 | 8959 | ||
@@ -8963,7 +8964,7 @@ static int tg3_halt(struct tg3 *tp, int kind, int silent) | |||
8963 | tg3_abort_hw(tp, silent); | 8964 | tg3_abort_hw(tp, silent); |
8964 | err = tg3_chip_reset(tp); | 8965 | err = tg3_chip_reset(tp); |
8965 | 8966 | ||
8966 | __tg3_set_mac_addr(tp, 0); | 8967 | __tg3_set_mac_addr(tp, false); |
8967 | 8968 | ||
8968 | tg3_write_sig_legacy(tp, kind); | 8969 | tg3_write_sig_legacy(tp, kind); |
8969 | tg3_write_sig_post_reset(tp, kind); | 8970 | tg3_write_sig_post_reset(tp, kind); |
@@ -8987,7 +8988,8 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p) | |||
8987 | { | 8988 | { |
8988 | struct tg3 *tp = netdev_priv(dev); | 8989 | struct tg3 *tp = netdev_priv(dev); |
8989 | struct sockaddr *addr = p; | 8990 | struct sockaddr *addr = p; |
8990 | int err = 0, skip_mac_1 = 0; | 8991 | int err = 0; |
8992 | bool skip_mac_1 = false; | ||
8991 | 8993 | ||
8992 | if (!is_valid_ether_addr(addr->sa_data)) | 8994 | if (!is_valid_ether_addr(addr->sa_data)) |
8993 | return -EADDRNOTAVAIL; | 8995 | return -EADDRNOTAVAIL; |
@@ -9008,7 +9010,7 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p) | |||
9008 | /* Skip MAC addr 1 if ASF is using it. */ | 9010 | /* Skip MAC addr 1 if ASF is using it. */ |
9009 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | 9011 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && |
9010 | !(addr1_high == 0 && addr1_low == 0)) | 9012 | !(addr1_high == 0 && addr1_low == 0)) |
9011 | skip_mac_1 = 1; | 9013 | skip_mac_1 = true; |
9012 | } | 9014 | } |
9013 | spin_lock_bh(&tp->lock); | 9015 | spin_lock_bh(&tp->lock); |
9014 | __tg3_set_mac_addr(tp, skip_mac_1); | 9016 | __tg3_set_mac_addr(tp, skip_mac_1); |
@@ -9427,7 +9429,7 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp) | |||
9427 | } | 9429 | } |
9428 | 9430 | ||
9429 | /* tp->lock is held. */ | 9431 | /* tp->lock is held. */ |
9430 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | 9432 | static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) |
9431 | { | 9433 | { |
9432 | u32 val, rdmac_mode; | 9434 | u32 val, rdmac_mode; |
9433 | int i, err, limit; | 9435 | int i, err, limit; |
@@ -9820,7 +9822,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9820 | tg3_rings_reset(tp); | 9822 | tg3_rings_reset(tp); |
9821 | 9823 | ||
9822 | /* Initialize MAC address and backoff seed. */ | 9824 | /* Initialize MAC address and backoff seed. */ |
9823 | __tg3_set_mac_addr(tp, 0); | 9825 | __tg3_set_mac_addr(tp, false); |
9824 | 9826 | ||
9825 | /* MTU + ethernet header + FCS + optional VLAN tag */ | 9827 | /* MTU + ethernet header + FCS + optional VLAN tag */ |
9826 | tw32(MAC_RX_MTU_SIZE, | 9828 | tw32(MAC_RX_MTU_SIZE, |
@@ -10271,7 +10273,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
10271 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) | 10273 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
10272 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | 10274 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
10273 | 10275 | ||
10274 | err = tg3_setup_phy(tp, 0); | 10276 | err = tg3_setup_phy(tp, false); |
10275 | if (err) | 10277 | if (err) |
10276 | return err; | 10278 | return err; |
10277 | 10279 | ||
@@ -10351,7 +10353,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
10351 | /* Called at device open time to get the chip ready for | 10353 | /* Called at device open time to get the chip ready for |
10352 | * packet processing. Invoked with tp->lock held. | 10354 | * packet processing. Invoked with tp->lock held. |
10353 | */ | 10355 | */ |
10354 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) | 10356 | static int tg3_init_hw(struct tg3 *tp, bool reset_phy) |
10355 | { | 10357 | { |
10356 | tg3_switch_clocks(tp); | 10358 | tg3_switch_clocks(tp); |
10357 | 10359 | ||
@@ -10612,7 +10614,7 @@ static void tg3_timer(unsigned long __opaque) | |||
10612 | phy_event = 1; | 10614 | phy_event = 1; |
10613 | 10615 | ||
10614 | if (phy_event) | 10616 | if (phy_event) |
10615 | tg3_setup_phy(tp, 0); | 10617 | tg3_setup_phy(tp, false); |
10616 | } else if (tg3_flag(tp, POLL_SERDES)) { | 10618 | } else if (tg3_flag(tp, POLL_SERDES)) { |
10617 | u32 mac_stat = tr32(MAC_STATUS); | 10619 | u32 mac_stat = tr32(MAC_STATUS); |
10618 | int need_setup = 0; | 10620 | int need_setup = 0; |
@@ -10635,7 +10637,7 @@ static void tg3_timer(unsigned long __opaque) | |||
10635 | tw32_f(MAC_MODE, tp->mac_mode); | 10637 | tw32_f(MAC_MODE, tp->mac_mode); |
10636 | udelay(40); | 10638 | udelay(40); |
10637 | } | 10639 | } |
10638 | tg3_setup_phy(tp, 0); | 10640 | tg3_setup_phy(tp, false); |
10639 | } | 10641 | } |
10640 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | 10642 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
10641 | tg3_flag(tp, 5780_CLASS)) { | 10643 | tg3_flag(tp, 5780_CLASS)) { |
@@ -10721,7 +10723,7 @@ static void tg3_timer_stop(struct tg3 *tp) | |||
10721 | /* Restart hardware after configuration changes, self-test, etc. | 10723 | /* Restart hardware after configuration changes, self-test, etc. |
10722 | * Invoked with tp->lock held. | 10724 | * Invoked with tp->lock held. |
10723 | */ | 10725 | */ |
10724 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | 10726 | static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) |
10725 | __releases(tp->lock) | 10727 | __releases(tp->lock) |
10726 | __acquires(tp->lock) | 10728 | __acquires(tp->lock) |
10727 | { | 10729 | { |
@@ -10771,7 +10773,7 @@ static void tg3_reset_task(struct work_struct *work) | |||
10771 | } | 10773 | } |
10772 | 10774 | ||
10773 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | 10775 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
10774 | err = tg3_init_hw(tp, 1); | 10776 | err = tg3_init_hw(tp, true); |
10775 | if (err) | 10777 | if (err) |
10776 | goto out; | 10778 | goto out; |
10777 | 10779 | ||
@@ -10941,7 +10943,7 @@ static int tg3_test_msi(struct tg3 *tp) | |||
10941 | tg3_full_lock(tp, 1); | 10943 | tg3_full_lock(tp, 1); |
10942 | 10944 | ||
10943 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 10945 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
10944 | err = tg3_init_hw(tp, 1); | 10946 | err = tg3_init_hw(tp, true); |
10945 | 10947 | ||
10946 | tg3_full_unlock(tp); | 10948 | tg3_full_unlock(tp); |
10947 | 10949 | ||
@@ -11814,7 +11816,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
11814 | tg3_warn_mgmt_link_flap(tp); | 11816 | tg3_warn_mgmt_link_flap(tp); |
11815 | 11817 | ||
11816 | if (netif_running(dev)) | 11818 | if (netif_running(dev)) |
11817 | tg3_setup_phy(tp, 1); | 11819 | tg3_setup_phy(tp, true); |
11818 | 11820 | ||
11819 | tg3_full_unlock(tp); | 11821 | tg3_full_unlock(tp); |
11820 | 11822 | ||
@@ -11970,7 +11972,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e | |||
11970 | 11972 | ||
11971 | if (netif_running(dev)) { | 11973 | if (netif_running(dev)) { |
11972 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 11974 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11973 | err = tg3_restart_hw(tp, 0); | 11975 | err = tg3_restart_hw(tp, false); |
11974 | if (!err) | 11976 | if (!err) |
11975 | tg3_netif_start(tp); | 11977 | tg3_netif_start(tp); |
11976 | } | 11978 | } |
@@ -12094,7 +12096,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam | |||
12094 | 12096 | ||
12095 | if (netif_running(dev)) { | 12097 | if (netif_running(dev)) { |
12096 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 12098 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
12097 | err = tg3_restart_hw(tp, 0); | 12099 | err = tg3_restart_hw(tp, false); |
12098 | if (!err) | 12100 | if (!err) |
12099 | tg3_netif_start(tp); | 12101 | tg3_netif_start(tp); |
12100 | } | 12102 | } |
@@ -13164,7 +13166,7 @@ static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) | |||
13164 | goto done; | 13166 | goto done; |
13165 | } | 13167 | } |
13166 | 13168 | ||
13167 | err = tg3_reset_hw(tp, 1); | 13169 | err = tg3_reset_hw(tp, true); |
13168 | if (err) { | 13170 | if (err) { |
13169 | data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED; | 13171 | data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
13170 | data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED; | 13172 | data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
@@ -13331,7 +13333,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, | |||
13331 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 13333 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
13332 | if (netif_running(dev)) { | 13334 | if (netif_running(dev)) { |
13333 | tg3_flag_set(tp, INIT_COMPLETE); | 13335 | tg3_flag_set(tp, INIT_COMPLETE); |
13334 | err2 = tg3_restart_hw(tp, 1); | 13336 | err2 = tg3_restart_hw(tp, true); |
13335 | if (!err2) | 13337 | if (!err2) |
13336 | tg3_netif_start(tp); | 13338 | tg3_netif_start(tp); |
13337 | } | 13339 | } |
@@ -13648,7 +13650,8 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |||
13648 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | 13650 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) |
13649 | { | 13651 | { |
13650 | struct tg3 *tp = netdev_priv(dev); | 13652 | struct tg3 *tp = netdev_priv(dev); |
13651 | int err, reset_phy = 0; | 13653 | int err; |
13654 | bool reset_phy = false; | ||
13652 | 13655 | ||
13653 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | 13656 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) |
13654 | return -EINVAL; | 13657 | return -EINVAL; |
@@ -13675,7 +13678,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |||
13675 | * breaks all requests to 256 bytes. | 13678 | * breaks all requests to 256 bytes. |
13676 | */ | 13679 | */ |
13677 | if (tg3_asic_rev(tp) == ASIC_REV_57766) | 13680 | if (tg3_asic_rev(tp) == ASIC_REV_57766) |
13678 | reset_phy = 1; | 13681 | reset_phy = true; |
13679 | 13682 | ||
13680 | err = tg3_restart_hw(tp, reset_phy); | 13683 | err = tg3_restart_hw(tp, reset_phy); |
13681 | 13684 | ||
@@ -16575,7 +16578,7 @@ out: | |||
16575 | } | 16578 | } |
16576 | 16579 | ||
16577 | static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, | 16580 | static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, |
16578 | int size, int to_device) | 16581 | int size, bool to_device) |
16579 | { | 16582 | { |
16580 | struct tg3_internal_buffer_desc test_desc; | 16583 | struct tg3_internal_buffer_desc test_desc; |
16581 | u32 sram_dma_descs; | 16584 | u32 sram_dma_descs; |
@@ -16775,7 +16778,7 @@ static int tg3_test_dma(struct tg3 *tp) | |||
16775 | p[i] = i; | 16778 | p[i] = i; |
16776 | 16779 | ||
16777 | /* Send the buffer to the chip. */ | 16780 | /* Send the buffer to the chip. */ |
16778 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | 16781 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); |
16779 | if (ret) { | 16782 | if (ret) { |
16780 | dev_err(&tp->pdev->dev, | 16783 | dev_err(&tp->pdev->dev, |
16781 | "%s: Buffer write failed. err = %d\n", | 16784 | "%s: Buffer write failed. err = %d\n", |
@@ -16798,7 +16801,7 @@ static int tg3_test_dma(struct tg3 *tp) | |||
16798 | } | 16801 | } |
16799 | #endif | 16802 | #endif |
16800 | /* Now read it back. */ | 16803 | /* Now read it back. */ |
16801 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | 16804 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); |
16802 | if (ret) { | 16805 | if (ret) { |
16803 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " | 16806 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
16804 | "err = %d\n", __func__, ret); | 16807 | "err = %d\n", __func__, ret); |
@@ -17479,7 +17482,7 @@ static int tg3_suspend(struct device *device) | |||
17479 | tg3_full_lock(tp, 0); | 17482 | tg3_full_lock(tp, 0); |
17480 | 17483 | ||
17481 | tg3_flag_set(tp, INIT_COMPLETE); | 17484 | tg3_flag_set(tp, INIT_COMPLETE); |
17482 | err2 = tg3_restart_hw(tp, 1); | 17485 | err2 = tg3_restart_hw(tp, true); |
17483 | if (err2) | 17486 | if (err2) |
17484 | goto out; | 17487 | goto out; |
17485 | 17488 | ||
@@ -17653,7 +17656,7 @@ static void tg3_io_resume(struct pci_dev *pdev) | |||
17653 | 17656 | ||
17654 | tg3_full_lock(tp, 0); | 17657 | tg3_full_lock(tp, 0); |
17655 | tg3_flag_set(tp, INIT_COMPLETE); | 17658 | tg3_flag_set(tp, INIT_COMPLETE); |
17656 | err = tg3_restart_hw(tp, 1); | 17659 | err = tg3_restart_hw(tp, true); |
17657 | if (err) { | 17660 | if (err) { |
17658 | tg3_full_unlock(tp); | 17661 | tg3_full_unlock(tp); |
17659 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | 17662 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); |