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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2015-05-26 07:13:43 -0400
committerFelipe Balbi <balbi@ti.com>2015-05-26 11:21:53 -0400
commit93fb9127cb63a3246b32d48fa273010764687862 (patch)
tree5fee26d03eeba0683b43a9a5a2c048f2bb4223d5
parente73d42f15f90614538edeb5d4102f847105f86f2 (diff)
usb: renesas_usbhs: Don't disable the pipe if Control write status stage
This patch fixes an issue that sometimes this controller is not able to complete the Control write status stage. This driver should enable DCPCTR.CCPL and PID_BUF to complete the status stage. However, if this driver detects the ctrl_stage interruption first before the control write data is received, this driver will clear the PID_BUF wrongly in the usbhsf_pio_try_pop(). To avoid this issue, this patch doesn't clear the PID_BUF in the usbhsf_pio_try_pop(). (Since also the privious code doesn't disable the PID_BUF after a control transfer was finished, this patch doesn't have any side efforts.) Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
-rw-r--r--drivers/usb/renesas_usbhs/fifo.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c
index 0bad84ebe9aa..c0f5c652d272 100644
--- a/drivers/usb/renesas_usbhs/fifo.c
+++ b/drivers/usb/renesas_usbhs/fifo.c
@@ -678,7 +678,14 @@ static int usbhsf_pio_try_pop(struct usbhs_pkt *pkt, int *is_done)
678 *is_done = 1; 678 *is_done = 1;
679 usbhsf_rx_irq_ctrl(pipe, 0); 679 usbhsf_rx_irq_ctrl(pipe, 0);
680 usbhs_pipe_running(pipe, 0); 680 usbhs_pipe_running(pipe, 0);
681 usbhs_pipe_disable(pipe); /* disable pipe first */ 681 /*
682 * If function mode, since this controller is possible to enter
683 * Control Write status stage at this timing, this driver
684 * should not disable the pipe. If such a case happens, this
685 * controller is not able to complete the status stage.
686 */
687 if (!usbhs_mod_is_host(priv) && !usbhs_pipe_is_dcp(pipe))
688 usbhs_pipe_disable(pipe); /* disable pipe first */
682 } 689 }
683 690
684 /* 691 /*