diff options
author | Steve Wise <swise@opengridcomputing.com> | 2010-06-23 11:46:55 -0400 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2010-08-08 02:08:47 -0400 |
commit | 93fb72e443b9fcbef598faa05478883952edca77 (patch) | |
tree | a9d58122bf50b6a988c40bc7a487363f8023492e | |
parent | 2d53056973079e6c2ffc0d7ae3afbdd3d4f18ae3 (diff) |
RDMA/cxgb4: Obtain RDMA QID ranges from LLD/FW
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
-rw-r--r-- | drivers/infiniband/hw/cxgb4/device.c | 9 | ||||
-rw-r--r-- | drivers/infiniband/hw/cxgb4/resource.c | 7 | ||||
-rw-r--r-- | drivers/infiniband/hw/cxgb4/t4.h | 2 |
3 files changed, 11 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/cxgb4/device.c b/drivers/infiniband/hw/cxgb4/device.c index d870f9c17c1e..9bbf491d5d9e 100644 --- a/drivers/infiniband/hw/cxgb4/device.c +++ b/drivers/infiniband/hw/cxgb4/device.c | |||
@@ -250,12 +250,17 @@ static int c4iw_rdev_open(struct c4iw_rdev *rdev) | |||
250 | rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density); | 250 | rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density); |
251 | rdev->cqmask = rdev->lldi.ucq_density - 1; | 251 | rdev->cqmask = rdev->lldi.ucq_density - 1; |
252 | PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d " | 252 | PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d " |
253 | "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x\n", | 253 | "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x " |
254 | "qp qid start %u size %u cq qid start %u size %u\n", | ||
254 | __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start, | 255 | __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start, |
255 | rdev->lldi.vr->stag.size, c4iw_num_stags(rdev), | 256 | rdev->lldi.vr->stag.size, c4iw_num_stags(rdev), |
256 | rdev->lldi.vr->pbl.start, | 257 | rdev->lldi.vr->pbl.start, |
257 | rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start, | 258 | rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start, |
258 | rdev->lldi.vr->rq.size); | 259 | rdev->lldi.vr->rq.size, |
260 | rdev->lldi.vr->qp.start, | ||
261 | rdev->lldi.vr->qp.size, | ||
262 | rdev->lldi.vr->cq.start, | ||
263 | rdev->lldi.vr->cq.size); | ||
259 | PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu " | 264 | PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu " |
260 | "qpmask 0x%x cqshift %lu cqmask 0x%x\n", | 265 | "qpmask 0x%x cqshift %lu cqmask 0x%x\n", |
261 | (unsigned)pci_resource_len(rdev->lldi.pdev, 2), | 266 | (unsigned)pci_resource_len(rdev->lldi.pdev, 2), |
diff --git a/drivers/infiniband/hw/cxgb4/resource.c b/drivers/infiniband/hw/cxgb4/resource.c index fb195d1d9015..83b23dfa250d 100644 --- a/drivers/infiniband/hw/cxgb4/resource.c +++ b/drivers/infiniband/hw/cxgb4/resource.c | |||
@@ -110,11 +110,12 @@ static int c4iw_init_qid_fifo(struct c4iw_rdev *rdev) | |||
110 | 110 | ||
111 | spin_lock_init(&rdev->resource.qid_fifo_lock); | 111 | spin_lock_init(&rdev->resource.qid_fifo_lock); |
112 | 112 | ||
113 | if (kfifo_alloc(&rdev->resource.qid_fifo, T4_MAX_QIDS * sizeof(u32), | 113 | if (kfifo_alloc(&rdev->resource.qid_fifo, rdev->lldi.vr->qp.size * |
114 | GFP_KERNEL)) | 114 | sizeof(u32), GFP_KERNEL)) |
115 | return -ENOMEM; | 115 | return -ENOMEM; |
116 | 116 | ||
117 | for (i = T4_QID_BASE; i < T4_QID_BASE + T4_MAX_QIDS; i++) | 117 | for (i = rdev->lldi.vr->qp.start; |
118 | i < rdev->lldi.vr->qp.start + rdev->lldi.vr->qp.size; i++) | ||
118 | if (!(i & rdev->qpmask)) | 119 | if (!(i & rdev->qpmask)) |
119 | kfifo_in(&rdev->resource.qid_fifo, | 120 | kfifo_in(&rdev->resource.qid_fifo, |
120 | (unsigned char *) &i, sizeof(u32)); | 121 | (unsigned char *) &i, sizeof(u32)); |
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h index aef55f42bea4..24f369046ef3 100644 --- a/drivers/infiniband/hw/cxgb4/t4.h +++ b/drivers/infiniband/hw/cxgb4/t4.h | |||
@@ -36,8 +36,6 @@ | |||
36 | #include "t4_msg.h" | 36 | #include "t4_msg.h" |
37 | #include "t4fw_ri_api.h" | 37 | #include "t4fw_ri_api.h" |
38 | 38 | ||
39 | #define T4_QID_BASE 1024 | ||
40 | #define T4_MAX_QIDS 256 | ||
41 | #define T4_MAX_NUM_QP (1<<16) | 39 | #define T4_MAX_NUM_QP (1<<16) |
42 | #define T4_MAX_NUM_CQ (1<<15) | 40 | #define T4_MAX_NUM_CQ (1<<15) |
43 | #define T4_MAX_NUM_PD (1<<15) | 41 | #define T4_MAX_NUM_PD (1<<15) |