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authorBruce Allan <bruce.w.allan@intel.com>2013-01-22 03:44:25 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2013-02-05 02:59:16 -0500
commit93b9f8bfd72818ddb540eb19333907989fb97043 (patch)
treec9d4869e8bf4417af67f53012ea56950c7ca4dc6
parentbdfe2da6aefd3961aac5c0cef76a030479e22f51 (diff)
e1000e: cosmetic move of #defines and function prototypes to the new phy.h
Move #defines and function prototypes which are applicable to all/most devices supported by the driver and are specific to the PHY component of each device to the new phy.h header file. These function prototypes can be used by other files in the driver and moving them to the PHY-specific file makes it clearer to which component they are applicable. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/e1000e/e1000.h95
-rw-r--r--drivers/net/ethernet/intel/e1000e/ethtool.c1
-rw-r--r--drivers/net/ethernet/intel/e1000e/hw.h89
-rw-r--r--drivers/net/ethernet/intel/e1000e/phy.c38
-rw-r--r--drivers/net/ethernet/intel/e1000e/phy.h242
5 files changed, 243 insertions, 222 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 0ad4ff1d8ec6..0573e15f6929 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -95,29 +95,6 @@ struct e1000_info;
95 95
96#define DEFAULT_JUMBO 9234 96#define DEFAULT_JUMBO 9234
97 97
98/* BM/HV Specific Registers */
99#define BM_PORT_CTRL_PAGE 769
100
101#define PHY_UPPER_SHIFT 21
102#define BM_PHY_REG(page, reg) \
103 (((reg) & MAX_PHY_REG_ADDRESS) |\
104 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
105 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
106
107/* BM PHY Copper Specific Status */
108#define BM_CS_STATUS 17
109#define BM_CS_STATUS_LINK_UP 0x0400
110#define BM_CS_STATUS_RESOLVED 0x0800
111#define BM_CS_STATUS_SPEED_MASK 0xC000
112#define BM_CS_STATUS_SPEED_1000 0x8000
113
114/* 82577 Mobile Phy Status Register */
115#define HV_M_STATUS 26
116#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
117#define HV_M_STATUS_SPEED_MASK 0x0300
118#define HV_M_STATUS_SPEED_1000 0x0200
119#define HV_M_STATUS_LINK_UP 0x0040
120
121/* Time to wait before putting the device into D3 if there's no link (in ms). */ 98/* Time to wait before putting the device into D3 if there's no link (in ms). */
122#define LINK_TIMEOUT 100 99#define LINK_TIMEOUT 100
123 100
@@ -538,79 +515,7 @@ extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
538 515
539extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 516extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
540 517
541extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
542extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
543extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); 518extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
544extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
545extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
546extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
547extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
548extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
549extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
550extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
551extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
552extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
553 u16 *data);
554extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
555extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
556extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
557extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
558 u16 data);
559extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
560extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
561extern s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
562extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
563extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
564extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
565extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
566extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
567extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
568extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
569extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
570extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
571extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
572 u16 *phy_reg);
573extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
574 u16 *phy_reg);
575extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
576extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
577extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
578extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
579extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
580 u16 data);
581extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
582extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
583 u16 *data);
584extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
585 u32 usec_interval, bool *success);
586extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
587extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
588extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
589extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
590extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
591extern s32 e1000e_check_downshift(struct e1000_hw *hw);
592extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
593extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
594 u16 *data);
595extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
596 u16 *data);
597extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
598extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
599 u16 data);
600extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
601 u16 data);
602extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
603extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
604extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
605extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
606extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
607extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
608
609extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
610extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
611extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
612extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
613extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
614extern void e1000e_ptp_init(struct e1000_adapter *adapter); 519extern void e1000e_ptp_init(struct e1000_adapter *adapter);
615extern void e1000e_ptp_remove(struct e1000_adapter *adapter); 520extern void e1000e_ptp_remove(struct e1000_adapter *adapter);
616 521
diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c
index c6c3e921686d..455e385120b4 100644
--- a/drivers/net/ethernet/intel/e1000e/ethtool.c
+++ b/drivers/net/ethernet/intel/e1000e/ethtool.c
@@ -1355,7 +1355,6 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1355 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg); 1355 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg);
1356 e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1); 1356 e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1);
1357 /* Enable loopback on the PHY */ 1357 /* Enable loopback on the PHY */
1358#define I82577_PHY_LBK_CTRL 19
1359 e1e_wphy(hw, I82577_PHY_LBK_CTRL, 0x8001); 1358 e1e_wphy(hw, I82577_PHY_LBK_CTRL, 0x8001);
1360 break; 1359 break;
1361 default: 1360 default:
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 0757f5bf26c4..5779ac4a4710 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -244,57 +244,6 @@ enum e1e_registers {
244 E1000_RXUDP = 0x0B638, /* Timesync Rx UDP Port - RW */ 244 E1000_RXUDP = 0x0B638, /* Timesync Rx UDP Port - RW */
245}; 245};
246 246
247#define E1000_MAX_PHY_ADDR 4
248
249/* IGP01E1000 Specific Registers */
250#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
251#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
252#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
253#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
254#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
255#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
256#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
257#define IGP_PAGE_SHIFT 5
258#define PHY_REG_MASK 0x1F
259
260#define BM_WUC_PAGE 800
261#define BM_WUC_ADDRESS_OPCODE 0x11
262#define BM_WUC_DATA_OPCODE 0x12
263#define BM_WUC_ENABLE_PAGE 769
264#define BM_WUC_ENABLE_REG 17
265#define BM_WUC_ENABLE_BIT (1 << 2)
266#define BM_WUC_HOST_WU_BIT (1 << 4)
267#define BM_WUC_ME_WU_BIT (1 << 5)
268
269#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
270#define IGP01E1000_PHY_POLARITY_MASK 0x0078
271
272#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
273#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
274
275#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
276
277#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
278#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
279#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
280
281#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
282
283#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
284#define IGP01E1000_PSSR_MDIX 0x0800
285#define IGP01E1000_PSSR_SPEED_MASK 0xC000
286#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
287
288#define IGP02E1000_PHY_CHANNEL_NUM 4
289#define IGP02E1000_PHY_AGC_A 0x11B1
290#define IGP02E1000_PHY_AGC_B 0x12B1
291#define IGP02E1000_PHY_AGC_C 0x14B1
292#define IGP02E1000_PHY_AGC_D 0x18B1
293
294#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
295#define IGP02E1000_AGC_LENGTH_MASK 0x7F
296#define IGP02E1000_AGC_RANGE 15
297
298/* manage.c */ 247/* manage.c */
299#define E1000_VFTA_ENTRY_SHIFT 5 248#define E1000_VFTA_ENTRY_SHIFT 5
300#define E1000_VFTA_ENTRY_MASK 0x7F 249#define E1000_VFTA_ENTRY_MASK 0x7F
@@ -320,43 +269,6 @@ enum e1e_registers {
320/* nvm.c */ 269/* nvm.c */
321#define E1000_STM_OPCODE 0xDB00 270#define E1000_STM_OPCODE 0xDB00
322 271
323#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
324#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
325#define E1000_KMRNCTRLSTA_REN 0x00200000
326#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
327#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
328#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
329#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
330#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
331#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
332#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
333#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
334#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
335
336#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
337#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
338#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
339#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
340
341/* IFE PHY Extended Status Control */
342#define IFE_PESC_POLARITY_REVERSED 0x0100
343
344/* IFE PHY Special Control */
345#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
346#define IFE_PSC_FORCE_POLARITY 0x0020
347
348/* IFE PHY Special Control and LED Control */
349#define IFE_PSCL_PROBE_MODE 0x0020
350#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
351#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
352
353/* IFE PHY MDIX Control */
354#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
355#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
356#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
357
358#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
359
360#define E1000_DEV_ID_82571EB_COPPER 0x105E 272#define E1000_DEV_ID_82571EB_COPPER 0x105E
361#define E1000_DEV_ID_82571EB_FIBER 0x105F 273#define E1000_DEV_ID_82571EB_FIBER 0x105F
362#define E1000_DEV_ID_82571EB_SERDES 0x1060 274#define E1000_DEV_ID_82571EB_SERDES 0x1060
@@ -764,6 +676,7 @@ struct e1000_host_mng_command_info {
764}; 676};
765 677
766#include "mac.h" 678#include "mac.h"
679#include "phy.h"
767 680
768/* Function pointers for the MAC. */ 681/* Function pointers for the MAC. */
769struct e1000_mac_operations { 682struct e1000_mac_operations {
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index 851685dd00d4..a5ff13b9ef86 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -53,44 +53,6 @@ static const u16 e1000_igp_2_cable_length_table[] = {
53#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 53#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
54 ARRAY_SIZE(e1000_igp_2_cable_length_table) 54 ARRAY_SIZE(e1000_igp_2_cable_length_table)
55 55
56#define BM_PHY_REG_PAGE(offset) \
57 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
58#define BM_PHY_REG_NUM(offset) \
59 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
60 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
61 ~MAX_PHY_REG_ADDRESS)))
62
63#define HV_INTC_FC_PAGE_START 768
64#define I82578_ADDR_REG 29
65#define I82577_ADDR_REG 16
66#define I82577_CFG_REG 22
67#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
68#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
69#define I82577_CTRL_REG 23
70
71/* 82577 specific PHY registers */
72#define I82577_PHY_CTRL_2 18
73#define I82577_PHY_STATUS_2 26
74#define I82577_PHY_DIAG_STATUS 31
75
76/* I82577 PHY Status 2 */
77#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
78#define I82577_PHY_STATUS2_MDIX 0x0800
79#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
80#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
81
82/* I82577 PHY Control 2 */
83#define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
84#define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
85#define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
86
87/* I82577 PHY Diagnostics Status */
88#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
89#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
90
91/* BM PHY Copper Specific Control 1 */
92#define BM_CS_CTRL1 16
93
94/** 56/**
95 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 57 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
96 * @hw: pointer to the HW structure 58 * @hw: pointer to the HW structure
diff --git a/drivers/net/ethernet/intel/e1000e/phy.h b/drivers/net/ethernet/intel/e1000e/phy.h
new file mode 100644
index 000000000000..f4f71b9991e3
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/phy.h
@@ -0,0 +1,242 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_PHY_H_
30#define _E1000E_PHY_H_
31
32s32 e1000e_check_downshift(struct e1000_hw *hw);
33s32 e1000_check_polarity_m88(struct e1000_hw *hw);
34s32 e1000_check_polarity_igp(struct e1000_hw *hw);
35s32 e1000_check_polarity_ife(struct e1000_hw *hw);
36s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
37s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
38s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
39s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
40s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
41s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
42s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
43s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
44s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
45s32 e1000e_get_phy_id(struct e1000_hw *hw);
46s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
47s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
48s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
49s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
50void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
51s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
52s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
53s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
54s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
55s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
56s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
57s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
58s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
59s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
60s32 e1000e_setup_copper_link(struct e1000_hw *hw);
61s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
62s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
63s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
64s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
65s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
66s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
67 u32 usec_interval, bool *success);
68s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
69enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
70s32 e1000e_determine_phy_address(struct e1000_hw *hw);
71s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
72s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
73s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
74s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
75s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
76s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
77void e1000_power_up_phy_copper(struct e1000_hw *hw);
78void e1000_power_down_phy_copper(struct e1000_hw *hw);
79s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
80s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
81s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
82s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
83s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
84s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
85s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
86s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
87s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
88s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
89s32 e1000_check_polarity_82577(struct e1000_hw *hw);
90s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
91s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
92s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
93
94#define E1000_MAX_PHY_ADDR 8
95
96/* IGP01E1000 Specific Registers */
97#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
98#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
99#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
100#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
101#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
102#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
103#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
104#define IGP_PAGE_SHIFT 5
105#define PHY_REG_MASK 0x1F
106
107/* BM/HV Specific Registers */
108#define BM_PORT_CTRL_PAGE 769
109#define BM_WUC_PAGE 800
110#define BM_WUC_ADDRESS_OPCODE 0x11
111#define BM_WUC_DATA_OPCODE 0x12
112#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
113#define BM_WUC_ENABLE_REG 17
114#define BM_WUC_ENABLE_BIT (1 << 2)
115#define BM_WUC_HOST_WU_BIT (1 << 4)
116#define BM_WUC_ME_WU_BIT (1 << 5)
117
118#define PHY_UPPER_SHIFT 21
119#define BM_PHY_REG(page, reg) \
120 (((reg) & MAX_PHY_REG_ADDRESS) |\
121 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
122 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
123#define BM_PHY_REG_PAGE(offset) \
124 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
125#define BM_PHY_REG_NUM(offset) \
126 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
127 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
128 ~MAX_PHY_REG_ADDRESS)))
129
130#define HV_INTC_FC_PAGE_START 768
131#define I82578_ADDR_REG 29
132#define I82577_ADDR_REG 16
133#define I82577_CFG_REG 22
134#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
135#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */
136#define I82577_CTRL_REG 23
137
138/* 82577 specific PHY registers */
139#define I82577_PHY_CTRL_2 18
140#define I82577_PHY_LBK_CTRL 19
141#define I82577_PHY_STATUS_2 26
142#define I82577_PHY_DIAG_STATUS 31
143
144/* I82577 PHY Status 2 */
145#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
146#define I82577_PHY_STATUS2_MDIX 0x0800
147#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
148#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
149
150/* I82577 PHY Control 2 */
151#define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
152#define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
153#define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
154
155/* I82577 PHY Diagnostics Status */
156#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
157#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
158
159/* BM PHY Copper Specific Control 1 */
160#define BM_CS_CTRL1 16
161
162/* BM PHY Copper Specific Status */
163#define BM_CS_STATUS 17
164#define BM_CS_STATUS_LINK_UP 0x0400
165#define BM_CS_STATUS_RESOLVED 0x0800
166#define BM_CS_STATUS_SPEED_MASK 0xC000
167#define BM_CS_STATUS_SPEED_1000 0x8000
168
169/* 82577 Mobile Phy Status Register */
170#define HV_M_STATUS 26
171#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
172#define HV_M_STATUS_SPEED_MASK 0x0300
173#define HV_M_STATUS_SPEED_1000 0x0200
174#define HV_M_STATUS_LINK_UP 0x0040
175
176#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
177#define IGP01E1000_PHY_POLARITY_MASK 0x0078
178
179#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
180#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
181
182#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
183
184#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
185#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
186#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
187
188#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
189
190#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
191#define IGP01E1000_PSSR_MDIX 0x0800
192#define IGP01E1000_PSSR_SPEED_MASK 0xC000
193#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
194
195#define IGP02E1000_PHY_CHANNEL_NUM 4
196#define IGP02E1000_PHY_AGC_A 0x11B1
197#define IGP02E1000_PHY_AGC_B 0x12B1
198#define IGP02E1000_PHY_AGC_C 0x14B1
199#define IGP02E1000_PHY_AGC_D 0x18B1
200
201#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
202#define IGP02E1000_AGC_LENGTH_MASK 0x7F
203#define IGP02E1000_AGC_RANGE 15
204
205#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
206
207#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
208#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
209#define E1000_KMRNCTRLSTA_REN 0x00200000
210#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
211#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
212#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
213#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
214#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
215#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
216#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
217#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
218#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
219
220#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
221#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
222#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
223#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
224
225/* IFE PHY Extended Status Control */
226#define IFE_PESC_POLARITY_REVERSED 0x0100
227
228/* IFE PHY Special Control */
229#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
230#define IFE_PSC_FORCE_POLARITY 0x0020
231
232/* IFE PHY Special Control and LED Control */
233#define IFE_PSCL_PROBE_MODE 0x0020
234#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
235#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
236
237/* IFE PHY MDIX Control */
238#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
239#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
240#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
241
242#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 11:35:41 -0500