Merge branch 'mvebu/fixes' into mvebu/soc

3 files changed, 35 insertions, 5 deletions

diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 461e726a7012..d965d0c0ef2d 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -126,7 +126,7 @@ static void __init i2c_quirk(void)
 
 static void __init mvebu_dt_init(void)
 {
-        if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
+        if (of_machine_is_compatible("marvell,armadaxp"))
                 i2c_quirk();
         if (of_machine_is_compatible("marvell,a375-db"))
                 external_abort_quirk();
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 2bdc3233abe2..044b51185fcc 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -400,6 +400,8 @@ int __init coherency_init(void)
                  type == COHERENCY_FABRIC_TYPE_ARMADA_380)
                 armada_375_380_coherency_init(np);
 
+        of_node_put(np);
+
         return 0;
 }
 
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index b61a3bcc2fa8..e048f6198d68 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -497,6 +497,34 @@ static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 #define orion_gpio_dbg_show NULL
 #endif
 
+static void orion_gpio_unmask_irq(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+        u32 reg_val;
+        u32 mask = d->mask;
+
+        irq_gc_lock(gc);
+        reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+        reg_val |= mask;
+        irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+        irq_gc_unlock(gc);
+}
+
+static void orion_gpio_mask_irq(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+        u32 mask = d->mask;
+        u32 reg_val;
+
+        irq_gc_lock(gc);
+        reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+        reg_val &= ~mask;
+        irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+        irq_gc_unlock(gc);
+}
+
 void __init orion_gpio_init(struct device_node *np,
                             int gpio_base, int ngpio,
                             void __iomem *base, int mask_offset,
@@ -565,8 +593,8 @@ void __init orion_gpio_init(struct device_node *np,
         ct = gc->chip_types;
         ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
         ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_mask = orion_gpio_mask_irq;
+        ct->chip.irq_unmask = orion_gpio_unmask_irq;
         ct->chip.irq_set_type = gpio_irq_set_type;
         ct->chip.name = ochip->chip.label;
 
@@ -575,8 +603,8 @@ void __init orion_gpio_init(struct device_node *np,
         ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
         ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
         ct->chip.irq_ack = irq_gc_ack_clr_bit;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_mask = orion_gpio_mask_irq;
+        ct->chip.irq_unmask = orion_gpio_unmask_irq;
         ct->chip.irq_set_type = gpio_irq_set_type;
         ct->handler = handle_edge_irq;
         ct->chip.name = ochip->chip.label;