diff options
author | Ondrej Zary <linux@rainbow-software.org> | 2011-05-09 17:39:51 -0400 |
---|---|---|
committer | Takashi Iwai <tiwai@suse.de> | 2011-05-10 03:31:45 -0400 |
commit | 938a1566b162aa485acd8dea2ebd92d92dfa0a45 (patch) | |
tree | a0aef0566ec4cf2f490191482016220ade365ffa | |
parent | 72587173cc31bb96db63e347b94ad0ef84878cea (diff) |
ALSA: fm801: convert TEA575x support to new interface
Use common functions to access TEA575x tuner - remove original read/write
functions and provide new pin manipulation functions instead.
Also convert the original triple implementation to a simple GPIO pin map.
Tested with SF256-PCP and SF64-PCR (added the GPIO pin for MO/ST signal
for them).
SF256-PCS untested (pin for MO/ST signal is a guess).
Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
-rw-r--r-- | sound/pci/fm801.c | 336 |
1 files changed, 57 insertions, 279 deletions
diff --git a/sound/pci/fm801.c b/sound/pci/fm801.c index f4dc1c77202b..1db5ead62a98 100644 --- a/sound/pci/fm801.c +++ b/sound/pci/fm801.c | |||
@@ -717,308 +717,86 @@ static int __devinit snd_fm801_pcm(struct fm801 *chip, int device, struct snd_pc | |||
717 | 717 | ||
718 | #ifdef TEA575X_RADIO | 718 | #ifdef TEA575X_RADIO |
719 | 719 | ||
720 | /* 256PCS GPIO numbers */ | 720 | /* GPIO to TEA575x maps */ |
721 | #define TEA_256PCS_DATA 1 | 721 | struct snd_fm801_tea575x_gpio { |
722 | #define TEA_256PCS_WRITE_ENABLE 2 /* inverted */ | 722 | u8 data, clk, wren, most; |
723 | #define TEA_256PCS_BUS_CLOCK 3 | 723 | }; |
724 | |||
725 | static void snd_fm801_tea575x_256pcs_write(struct snd_tea575x *tea, unsigned int val) | ||
726 | { | ||
727 | struct fm801 *chip = tea->private_data; | ||
728 | unsigned short reg; | ||
729 | int i = 25; | ||
730 | |||
731 | spin_lock_irq(&chip->reg_lock); | ||
732 | reg = inw(FM801_REG(chip, GPIO_CTRL)); | ||
733 | /* use GPIO lines and set write enable bit */ | ||
734 | reg |= FM801_GPIO_GS(TEA_256PCS_DATA) | | ||
735 | FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) | | ||
736 | FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK); | ||
737 | /* all of lines are in the write direction */ | ||
738 | /* clear data and clock lines */ | ||
739 | reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) | | ||
740 | FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) | | ||
741 | FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) | | ||
742 | FM801_GPIO_GP(TEA_256PCS_DATA) | | ||
743 | FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) | | ||
744 | FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE)); | ||
745 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
746 | udelay(1); | ||
747 | |||
748 | while (i--) { | ||
749 | if (val & (1 << i)) | ||
750 | reg |= FM801_GPIO_GP(TEA_256PCS_DATA); | ||
751 | else | ||
752 | reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA); | ||
753 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
754 | udelay(1); | ||
755 | reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK); | ||
756 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
757 | reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK); | ||
758 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
759 | udelay(1); | ||
760 | } | ||
761 | 724 | ||
762 | /* and reset the write enable bit */ | 725 | static struct snd_fm801_tea575x_gpio snd_fm801_tea575x_gpios[] = { |
763 | reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) | | 726 | { .data = 1, .clk = 3, .wren = 2, .most = 0 }, /* SF256-PCS */ |
764 | FM801_GPIO_GP(TEA_256PCS_DATA); | 727 | { .data = 1, .clk = 0, .wren = 2, .most = 3 }, /* SF256-PCP */ |
765 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | 728 | { .data = 2, .clk = 0, .wren = 1, .most = 3 }, /* SF64-PCR */ |
766 | spin_unlock_irq(&chip->reg_lock); | 729 | }; |
767 | } | ||
768 | 730 | ||
769 | static unsigned int snd_fm801_tea575x_256pcs_read(struct snd_tea575x *tea) | 731 | static void snd_fm801_tea575x_set_pins(struct snd_tea575x *tea, u8 pins) |
770 | { | 732 | { |
771 | struct fm801 *chip = tea->private_data; | 733 | struct fm801 *chip = tea->private_data; |
772 | unsigned short reg; | 734 | unsigned short reg = inw(FM801_REG(chip, GPIO_CTRL)); |
773 | unsigned int val = 0; | 735 | struct snd_fm801_tea575x_gpio gpio = snd_fm801_tea575x_gpios[(chip->tea575x_tuner & TUNER_TYPE_MASK) - 1]; |
774 | int i; | ||
775 | |||
776 | spin_lock_irq(&chip->reg_lock); | ||
777 | reg = inw(FM801_REG(chip, GPIO_CTRL)); | ||
778 | /* use GPIO lines, set data direction to input */ | ||
779 | reg |= FM801_GPIO_GS(TEA_256PCS_DATA) | | ||
780 | FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) | | ||
781 | FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) | | ||
782 | FM801_GPIO_GD(TEA_256PCS_DATA) | | ||
783 | FM801_GPIO_GP(TEA_256PCS_DATA) | | ||
784 | FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE); | ||
785 | /* all of lines are in the write direction, except data */ | ||
786 | /* clear data, write enable and clock lines */ | ||
787 | reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) | | ||
788 | FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) | | ||
789 | FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK)); | ||
790 | |||
791 | for (i = 0; i < 24; i++) { | ||
792 | reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK); | ||
793 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
794 | udelay(1); | ||
795 | reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK); | ||
796 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
797 | udelay(1); | ||
798 | val <<= 1; | ||
799 | if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA)) | ||
800 | val |= 1; | ||
801 | } | ||
802 | |||
803 | spin_unlock_irq(&chip->reg_lock); | ||
804 | |||
805 | return val; | ||
806 | } | ||
807 | |||
808 | /* 256PCPR GPIO numbers */ | ||
809 | #define TEA_256PCPR_BUS_CLOCK 0 | ||
810 | #define TEA_256PCPR_DATA 1 | ||
811 | #define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */ | ||
812 | 736 | ||
813 | static void snd_fm801_tea575x_256pcpr_write(struct snd_tea575x *tea, unsigned int val) | 737 | reg &= ~(FM801_GPIO_GP(gpio.data) | |
814 | { | 738 | FM801_GPIO_GP(gpio.clk) | |
815 | struct fm801 *chip = tea->private_data; | 739 | FM801_GPIO_GP(gpio.wren)); |
816 | unsigned short reg; | ||
817 | int i = 25; | ||
818 | 740 | ||
819 | spin_lock_irq(&chip->reg_lock); | 741 | reg |= (pins & TEA575X_DATA) ? FM801_GPIO_GP(gpio.data) : 0; |
820 | reg = inw(FM801_REG(chip, GPIO_CTRL)); | 742 | reg |= (pins & TEA575X_CLK) ? FM801_GPIO_GP(gpio.clk) : 0; |
821 | /* use GPIO lines and set write enable bit */ | 743 | /* WRITE_ENABLE is inverted */ |
822 | reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) | | 744 | reg |= (pins & TEA575X_WREN) ? 0 : FM801_GPIO_GP(gpio.wren); |
823 | FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) | | ||
824 | FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK); | ||
825 | /* all of lines are in the write direction */ | ||
826 | /* clear data and clock lines */ | ||
827 | reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) | | ||
828 | FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) | | ||
829 | FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) | | ||
830 | FM801_GPIO_GP(TEA_256PCPR_DATA) | | ||
831 | FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) | | ||
832 | FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE)); | ||
833 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
834 | udelay(1); | ||
835 | |||
836 | while (i--) { | ||
837 | if (val & (1 << i)) | ||
838 | reg |= FM801_GPIO_GP(TEA_256PCPR_DATA); | ||
839 | else | ||
840 | reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA); | ||
841 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
842 | udelay(1); | ||
843 | reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK); | ||
844 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
845 | reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK); | ||
846 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
847 | udelay(1); | ||
848 | } | ||
849 | 745 | ||
850 | /* and reset the write enable bit */ | ||
851 | reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) | | ||
852 | FM801_GPIO_GP(TEA_256PCPR_DATA); | ||
853 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | 746 | outw(reg, FM801_REG(chip, GPIO_CTRL)); |
854 | spin_unlock_irq(&chip->reg_lock); | ||
855 | } | 747 | } |
856 | 748 | ||
857 | static unsigned int snd_fm801_tea575x_256pcpr_read(struct snd_tea575x *tea) | 749 | static u8 snd_fm801_tea575x_get_pins(struct snd_tea575x *tea) |
858 | { | 750 | { |
859 | struct fm801 *chip = tea->private_data; | 751 | struct fm801 *chip = tea->private_data; |
860 | unsigned short reg; | 752 | unsigned short reg = inw(FM801_REG(chip, GPIO_CTRL)); |
861 | unsigned int val = 0; | 753 | struct snd_fm801_tea575x_gpio gpio = snd_fm801_tea575x_gpios[(chip->tea575x_tuner & TUNER_TYPE_MASK) - 1]; |
862 | int i; | ||
863 | |||
864 | spin_lock_irq(&chip->reg_lock); | ||
865 | reg = inw(FM801_REG(chip, GPIO_CTRL)); | ||
866 | /* use GPIO lines, set data direction to input */ | ||
867 | reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) | | ||
868 | FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) | | ||
869 | FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) | | ||
870 | FM801_GPIO_GD(TEA_256PCPR_DATA) | | ||
871 | FM801_GPIO_GP(TEA_256PCPR_DATA) | | ||
872 | FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE); | ||
873 | /* all of lines are in the write direction, except data */ | ||
874 | /* clear data, write enable and clock lines */ | ||
875 | reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) | | ||
876 | FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) | | ||
877 | FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK)); | ||
878 | |||
879 | for (i = 0; i < 24; i++) { | ||
880 | reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK); | ||
881 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
882 | udelay(1); | ||
883 | reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK); | ||
884 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
885 | udelay(1); | ||
886 | val <<= 1; | ||
887 | if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA)) | ||
888 | val |= 1; | ||
889 | } | ||
890 | |||
891 | spin_unlock_irq(&chip->reg_lock); | ||
892 | 754 | ||
893 | return val; | 755 | return (reg & FM801_GPIO_GP(gpio.data)) ? TEA575X_DATA : 0 | |
756 | (reg & FM801_GPIO_GP(gpio.most)) ? TEA575X_MOST : 0; | ||
894 | } | 757 | } |
895 | 758 | ||
896 | /* 64PCR GPIO numbers */ | 759 | static void snd_fm801_tea575x_set_direction(struct snd_tea575x *tea, bool output) |
897 | #define TEA_64PCR_BUS_CLOCK 0 | ||
898 | #define TEA_64PCR_WRITE_ENABLE 1 /* inverted */ | ||
899 | #define TEA_64PCR_DATA 2 | ||
900 | |||
901 | static void snd_fm801_tea575x_64pcr_write(struct snd_tea575x *tea, unsigned int val) | ||
902 | { | 760 | { |
903 | struct fm801 *chip = tea->private_data; | 761 | struct fm801 *chip = tea->private_data; |
904 | unsigned short reg; | 762 | unsigned short reg = inw(FM801_REG(chip, GPIO_CTRL)); |
905 | int i = 25; | 763 | struct snd_fm801_tea575x_gpio gpio = snd_fm801_tea575x_gpios[(chip->tea575x_tuner & TUNER_TYPE_MASK) - 1]; |
906 | 764 | ||
907 | spin_lock_irq(&chip->reg_lock); | ||
908 | reg = inw(FM801_REG(chip, GPIO_CTRL)); | ||
909 | /* use GPIO lines and set write enable bit */ | 765 | /* use GPIO lines and set write enable bit */ |
910 | reg |= FM801_GPIO_GS(TEA_64PCR_DATA) | | 766 | reg |= FM801_GPIO_GS(gpio.data) | |
911 | FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) | | 767 | FM801_GPIO_GS(gpio.wren) | |
912 | FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK); | 768 | FM801_GPIO_GS(gpio.clk) | |
913 | /* all of lines are in the write direction */ | 769 | FM801_GPIO_GS(gpio.most); |
914 | /* clear data and clock lines */ | 770 | if (output) { |
915 | reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) | | 771 | /* all of lines are in the write direction */ |
916 | FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) | | 772 | /* clear data and clock lines */ |
917 | FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) | | 773 | reg &= ~(FM801_GPIO_GD(gpio.data) | |
918 | FM801_GPIO_GP(TEA_64PCR_DATA) | | 774 | FM801_GPIO_GD(gpio.wren) | |
919 | FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) | | 775 | FM801_GPIO_GD(gpio.clk) | |
920 | FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE)); | 776 | FM801_GPIO_GP(gpio.data) | |
921 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | 777 | FM801_GPIO_GP(gpio.clk) | |
922 | udelay(1); | 778 | FM801_GPIO_GP(gpio.wren)); |
923 | 779 | } else { | |
924 | while (i--) { | 780 | /* use GPIO lines, set data direction to input */ |
925 | if (val & (1 << i)) | 781 | reg |= FM801_GPIO_GD(gpio.data) | |
926 | reg |= FM801_GPIO_GP(TEA_64PCR_DATA); | 782 | FM801_GPIO_GD(gpio.most) | |
927 | else | 783 | FM801_GPIO_GP(gpio.data) | |
928 | reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA); | 784 | FM801_GPIO_GP(gpio.most) | |
929 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | 785 | FM801_GPIO_GP(gpio.wren); |
930 | udelay(1); | 786 | /* all of lines are in the write direction, except data */ |
931 | reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK); | 787 | /* clear data, write enable and clock lines */ |
932 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | 788 | reg &= ~(FM801_GPIO_GD(gpio.wren) | |
933 | reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK); | 789 | FM801_GPIO_GD(gpio.clk) | |
934 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | 790 | FM801_GPIO_GP(gpio.clk)); |
935 | udelay(1); | ||
936 | } | ||
937 | |||
938 | /* and reset the write enable bit */ | ||
939 | reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) | | ||
940 | FM801_GPIO_GP(TEA_64PCR_DATA); | ||
941 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
942 | spin_unlock_irq(&chip->reg_lock); | ||
943 | } | ||
944 | |||
945 | static unsigned int snd_fm801_tea575x_64pcr_read(struct snd_tea575x *tea) | ||
946 | { | ||
947 | struct fm801 *chip = tea->private_data; | ||
948 | unsigned short reg; | ||
949 | unsigned int val = 0; | ||
950 | int i; | ||
951 | |||
952 | spin_lock_irq(&chip->reg_lock); | ||
953 | reg = inw(FM801_REG(chip, GPIO_CTRL)); | ||
954 | /* use GPIO lines, set data direction to input */ | ||
955 | reg |= FM801_GPIO_GS(TEA_64PCR_DATA) | | ||
956 | FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) | | ||
957 | FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) | | ||
958 | FM801_GPIO_GD(TEA_64PCR_DATA) | | ||
959 | FM801_GPIO_GP(TEA_64PCR_DATA) | | ||
960 | FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE); | ||
961 | /* all of lines are in the write direction, except data */ | ||
962 | /* clear data, write enable and clock lines */ | ||
963 | reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) | | ||
964 | FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) | | ||
965 | FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK)); | ||
966 | |||
967 | for (i = 0; i < 24; i++) { | ||
968 | reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK); | ||
969 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
970 | udelay(1); | ||
971 | reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK); | ||
972 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | ||
973 | udelay(1); | ||
974 | val <<= 1; | ||
975 | if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA)) | ||
976 | val |= 1; | ||
977 | } | 791 | } |
978 | 792 | ||
979 | spin_unlock_irq(&chip->reg_lock); | ||
980 | |||
981 | return val; | ||
982 | } | ||
983 | |||
984 | static void snd_fm801_tea575x_64pcr_mute(struct snd_tea575x *tea, | ||
985 | unsigned int mute) | ||
986 | { | ||
987 | struct fm801 *chip = tea->private_data; | ||
988 | unsigned short reg; | ||
989 | |||
990 | spin_lock_irq(&chip->reg_lock); | ||
991 | |||
992 | reg = inw(FM801_REG(chip, GPIO_CTRL)); | ||
993 | if (mute) | ||
994 | /* 0xf800 (mute) */ | ||
995 | reg &= ~FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE); | ||
996 | else | ||
997 | /* 0xf802 (unmute) */ | ||
998 | reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE); | ||
999 | outw(reg, FM801_REG(chip, GPIO_CTRL)); | 793 | outw(reg, FM801_REG(chip, GPIO_CTRL)); |
1000 | udelay(1); | ||
1001 | |||
1002 | spin_unlock_irq(&chip->reg_lock); | ||
1003 | } | 794 | } |
1004 | 795 | ||
1005 | static struct snd_tea575x_ops snd_fm801_tea_ops[3] = { | 796 | static struct snd_tea575x_ops snd_fm801_tea_ops = { |
1006 | { | 797 | .set_pins = snd_fm801_tea575x_set_pins, |
1007 | /* 1 = MediaForte 256-PCS */ | 798 | .get_pins = snd_fm801_tea575x_get_pins, |
1008 | .write = snd_fm801_tea575x_256pcs_write, | 799 | .set_direction = snd_fm801_tea575x_set_direction, |
1009 | .read = snd_fm801_tea575x_256pcs_read, | ||
1010 | }, | ||
1011 | { | ||
1012 | /* 2 = MediaForte 256-PCPR */ | ||
1013 | .write = snd_fm801_tea575x_256pcpr_write, | ||
1014 | .read = snd_fm801_tea575x_256pcpr_read, | ||
1015 | }, | ||
1016 | { | ||
1017 | /* 3 = MediaForte 64-PCR */ | ||
1018 | .write = snd_fm801_tea575x_64pcr_write, | ||
1019 | .read = snd_fm801_tea575x_64pcr_read, | ||
1020 | .mute = snd_fm801_tea575x_64pcr_mute, | ||
1021 | } | ||
1022 | }; | 800 | }; |
1023 | #endif | 801 | #endif |
1024 | 802 | ||
@@ -1456,7 +1234,7 @@ static int __devinit snd_fm801_create(struct snd_card *card, | |||
1456 | chip->tea.card = card; | 1234 | chip->tea.card = card; |
1457 | chip->tea.freq_fixup = 10700; | 1235 | chip->tea.freq_fixup = 10700; |
1458 | chip->tea.private_data = chip; | 1236 | chip->tea.private_data = chip; |
1459 | chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & TUNER_TYPE_MASK) - 1]; | 1237 | chip->tea.ops = &snd_fm801_tea_ops; |
1460 | snd_tea575x_init(&chip->tea); | 1238 | snd_tea575x_init(&chip->tea); |
1461 | } | 1239 | } |
1462 | #endif | 1240 | #endif |