diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2014-04-19 08:03:37 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-23 09:11:04 -0400 |
commit | 92df0f8b350f28ceebef7e0bc785816d84df626b (patch) | |
tree | 033b9a12efca77fb1ceba34ce1e55eb44c60d1d5 | |
parent | fcfe2285e5c53cb33309f946ba1fccd6b5db64df (diff) |
MIPS: math-emu: Convert debug printks to pr_debug getting.
And another bunch of #ifdefs bite the dust.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/math-emu/cp1emu.c | 16 | ||||
-rw-r--r-- | arch/mips/math-emu/dsemul.c | 9 |
2 files changed, 9 insertions, 16 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 972a7e23737a..3a0dfa4feadd 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c | |||
@@ -1119,11 +1119,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, | |||
1119 | value = ctx->fcr31; | 1119 | value = ctx->fcr31; |
1120 | value = (value & ~FPU_CSR_RM) | | 1120 | value = (value & ~FPU_CSR_RM) | |
1121 | mips_rm[modeindex(value)]; | 1121 | mips_rm[modeindex(value)]; |
1122 | #ifdef CSRTRACE | 1122 | pr_debug("%p gpr[%d]<-csr=%08x\n", |
1123 | printk("%p gpr[%d]<-csr=%08x\n", | 1123 | (void *) (xcp->cp0_epc), |
1124 | (void *) (xcp->cp0_epc), | 1124 | MIPSInst_RT(ir), value); |
1125 | MIPSInst_RT(ir), value); | ||
1126 | #endif | ||
1127 | } | 1125 | } |
1128 | else if (MIPSInst_RD(ir) == FPCREG_RID) | 1126 | else if (MIPSInst_RD(ir) == FPCREG_RID) |
1129 | value = 0; | 1127 | value = 0; |
@@ -1146,11 +1144,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, | |||
1146 | /* we only have one writable control reg | 1144 | /* we only have one writable control reg |
1147 | */ | 1145 | */ |
1148 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | 1146 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
1149 | #ifdef CSRTRACE | 1147 | pr_debug("%p gpr[%d]->csr=%08x\n", |
1150 | printk("%p gpr[%d]->csr=%08x\n", | 1148 | (void *) (xcp->cp0_epc), |
1151 | (void *) (xcp->cp0_epc), | 1149 | MIPSInst_RT(ir), value); |
1152 | MIPSInst_RT(ir), value); | ||
1153 | #endif | ||
1154 | 1150 | ||
1155 | /* | 1151 | /* |
1156 | * Don't write reserved bits, | 1152 | * Don't write reserved bits, |
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index c6e879c59a7f..4f514f3724cb 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c | |||
@@ -44,10 +44,8 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) | |||
44 | clear_delay_slot(regs); | 44 | clear_delay_slot(regs); |
45 | return 0; | 45 | return 0; |
46 | } | 46 | } |
47 | #ifdef DSEMUL_TRACE | ||
48 | printk("dsemul %lx %lx\n", regs->cp0_epc, cpc); | ||
49 | 47 | ||
50 | #endif | 48 | pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc); |
51 | 49 | ||
52 | /* | 50 | /* |
53 | * The strategy is to push the instruction onto the user stack | 51 | * The strategy is to push the instruction onto the user stack |
@@ -149,9 +147,8 @@ int do_dsemulret(struct pt_regs *xcp) | |||
149 | * emulating the branch delay instruction. | 147 | * emulating the branch delay instruction. |
150 | */ | 148 | */ |
151 | 149 | ||
152 | #ifdef DSEMUL_TRACE | 150 | pr_debug("dsemulret\n"); |
153 | printk("dsemulret\n"); | 151 | |
154 | #endif | ||
155 | if (__get_user(epc, &fr->epc)) { /* Saved EPC */ | 152 | if (__get_user(epc, &fr->epc)) { /* Saved EPC */ |
156 | /* This is not a good situation to be in */ | 153 | /* This is not a good situation to be in */ |
157 | force_sig(SIGBUS, current); | 154 | force_sig(SIGBUS, current); |