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authorSteve Muckle <smuckle@codeaurora.org>2010-02-11 14:50:40 -0500
committerDaniel Walker <dwalker@codeaurora.org>2010-10-08 18:12:40 -0400
commit9161d303af547653c66dab4e235b6fd0c3ac6148 (patch)
treee6440360226316622b6a65231ea6229d44b26cb5
parentf880c5649ec7a831a45cd254e9ecf9bd25b17dba (diff)
msm: 8x60: gic initialization fixup for RUMI
On RUMI platform STIs are not enabled by default, contrary to the GIC spec. The bits for STIs in the enable/enable clear registers are also RW instead of RO. STIs need to be enabled at initialization time. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index d30ead145001..e7feb99b5cfe 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -19,6 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/irq.h>
22 23
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
@@ -41,9 +42,28 @@ static void __init msm8x60_map_io(void)
41 42
42static void __init msm8x60_init_irq(void) 43static void __init msm8x60_init_irq(void)
43{ 44{
45 unsigned int i;
46
44 gic_dist_init(0, MSM_QGIC_DIST_BASE, 1); 47 gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
45 gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; 48 gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
46 gic_cpu_init(0, MSM_QGIC_CPU_BASE); 49 gic_cpu_init(0, MSM_QGIC_CPU_BASE);
50
51 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
52 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
53
54 /* RUMI does not adhere to GIC spec by enabling STIs by default.
55 * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
56 */
57 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
58
59 /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
60 * as they are configured as level, which does not play nice with
61 * handle_percpu_irq.
62 */
63 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
64 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
65 set_irq_handler(i, handle_percpu_irq);
66 }
47} 67}
48 68
49static void __init msm8x60_init(void) 69static void __init msm8x60_init(void)