diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-04-02 20:18:57 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-04-02 20:18:57 -0400 |
commit | 8f778bbc542ddf8f6243b21d6aca087e709cabdc (patch) | |
tree | 311136038098380d291763397612dd4a5a4cadc8 | |
parent | 4e8a4830dc9f0883d5302b871adb9e6179338d24 (diff) | |
parent | 51b52fac9b4ece9ec0c27a39b0ae1b3b4a829df9 (diff) |
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"One drm core fix, one exynos regression fix, two sets of radeon fixes
(Alex was a bit behind last week), and two i915 fixes.
Nothing too serious we seem to have calmed down i915 since last week"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon: fix wait in radeon_mn_invalidate_range_start
drm/radeon: add extra check in radeon_ttm_tt_unpin_userptr
drm: Exynos: Respect framebuffer pitch for FIMD/Mixer
drm/i915: Reject the colorkey ioctls for primary and cursor planes
drm/i915: Skip allocating shadow batch for 0-length batches
drm/radeon: programm the VCE fw BAR as well
drm/radeon: always dump the ring content if it's available
radeon: Do not directly dereference pointers to BIOS area.
drm/radeon/dpm: fix 120hz handling harder
drm/edid: set ELD for firmware and debugfs override EDIDs
-rw-r--r-- | drivers/gpu/drm/drm_edid_load.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/drm_probe_helper.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_fimd.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_mixer.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_sprite.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/cikd.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_bios.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_mn.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_pm.c | 22 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_ring.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_ttm.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/vce_v2_0.c | 3 |
14 files changed, 58 insertions, 29 deletions
diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c index 732cb6f8e653..4c0aa97aaf03 100644 --- a/drivers/gpu/drm/drm_edid_load.c +++ b/drivers/gpu/drm/drm_edid_load.c | |||
@@ -287,6 +287,7 @@ int drm_load_edid_firmware(struct drm_connector *connector) | |||
287 | 287 | ||
288 | drm_mode_connector_update_edid_property(connector, edid); | 288 | drm_mode_connector_update_edid_property(connector, edid); |
289 | ret = drm_add_edid_modes(connector, edid); | 289 | ret = drm_add_edid_modes(connector, edid); |
290 | drm_edid_to_eld(connector, edid); | ||
290 | kfree(edid); | 291 | kfree(edid); |
291 | 292 | ||
292 | return ret; | 293 | return ret; |
diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index 6591d48c1b9d..3fee587bc284 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c | |||
@@ -174,6 +174,7 @@ static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect | |||
174 | struct edid *edid = (struct edid *) connector->edid_blob_ptr->data; | 174 | struct edid *edid = (struct edid *) connector->edid_blob_ptr->data; |
175 | 175 | ||
176 | count = drm_add_edid_modes(connector, edid); | 176 | count = drm_add_edid_modes(connector, edid); |
177 | drm_edid_to_eld(connector, edid); | ||
177 | } else | 178 | } else |
178 | count = (*connector_funcs->get_modes)(connector); | 179 | count = (*connector_funcs->get_modes)(connector); |
179 | } | 180 | } |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index c300e22da8ac..33a10ce967ea 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c | |||
@@ -147,6 +147,7 @@ struct fimd_win_data { | |||
147 | unsigned int ovl_height; | 147 | unsigned int ovl_height; |
148 | unsigned int fb_width; | 148 | unsigned int fb_width; |
149 | unsigned int fb_height; | 149 | unsigned int fb_height; |
150 | unsigned int fb_pitch; | ||
150 | unsigned int bpp; | 151 | unsigned int bpp; |
151 | unsigned int pixel_format; | 152 | unsigned int pixel_format; |
152 | dma_addr_t dma_addr; | 153 | dma_addr_t dma_addr; |
@@ -532,13 +533,14 @@ static void fimd_win_mode_set(struct exynos_drm_crtc *crtc, | |||
532 | win_data->offset_y = plane->crtc_y; | 533 | win_data->offset_y = plane->crtc_y; |
533 | win_data->ovl_width = plane->crtc_width; | 534 | win_data->ovl_width = plane->crtc_width; |
534 | win_data->ovl_height = plane->crtc_height; | 535 | win_data->ovl_height = plane->crtc_height; |
536 | win_data->fb_pitch = plane->pitch; | ||
535 | win_data->fb_width = plane->fb_width; | 537 | win_data->fb_width = plane->fb_width; |
536 | win_data->fb_height = plane->fb_height; | 538 | win_data->fb_height = plane->fb_height; |
537 | win_data->dma_addr = plane->dma_addr[0] + offset; | 539 | win_data->dma_addr = plane->dma_addr[0] + offset; |
538 | win_data->bpp = plane->bpp; | 540 | win_data->bpp = plane->bpp; |
539 | win_data->pixel_format = plane->pixel_format; | 541 | win_data->pixel_format = plane->pixel_format; |
540 | win_data->buf_offsize = (plane->fb_width - plane->crtc_width) * | 542 | win_data->buf_offsize = |
541 | (plane->bpp >> 3); | 543 | plane->pitch - (plane->crtc_width * (plane->bpp >> 3)); |
542 | win_data->line_size = plane->crtc_width * (plane->bpp >> 3); | 544 | win_data->line_size = plane->crtc_width * (plane->bpp >> 3); |
543 | 545 | ||
544 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | 546 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", |
@@ -704,7 +706,7 @@ static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos) | |||
704 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); | 706 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
705 | 707 | ||
706 | /* buffer end address */ | 708 | /* buffer end address */ |
707 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); | 709 | size = win_data->fb_pitch * win_data->ovl_height * (win_data->bpp >> 3); |
708 | val = (unsigned long)(win_data->dma_addr + size); | 710 | val = (unsigned long)(win_data->dma_addr + size); |
709 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); | 711 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
710 | 712 | ||
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 3518bc4654c5..2e3bc57ea50e 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c | |||
@@ -55,6 +55,7 @@ struct hdmi_win_data { | |||
55 | unsigned int fb_x; | 55 | unsigned int fb_x; |
56 | unsigned int fb_y; | 56 | unsigned int fb_y; |
57 | unsigned int fb_width; | 57 | unsigned int fb_width; |
58 | unsigned int fb_pitch; | ||
58 | unsigned int fb_height; | 59 | unsigned int fb_height; |
59 | unsigned int src_width; | 60 | unsigned int src_width; |
60 | unsigned int src_height; | 61 | unsigned int src_height; |
@@ -438,7 +439,7 @@ static void vp_video_buffer(struct mixer_context *ctx, int win) | |||
438 | } else { | 439 | } else { |
439 | luma_addr[0] = win_data->dma_addr; | 440 | luma_addr[0] = win_data->dma_addr; |
440 | chroma_addr[0] = win_data->dma_addr | 441 | chroma_addr[0] = win_data->dma_addr |
441 | + (win_data->fb_width * win_data->fb_height); | 442 | + (win_data->fb_pitch * win_data->fb_height); |
442 | } | 443 | } |
443 | 444 | ||
444 | if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE) { | 445 | if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE) { |
@@ -447,8 +448,8 @@ static void vp_video_buffer(struct mixer_context *ctx, int win) | |||
447 | luma_addr[1] = luma_addr[0] + 0x40; | 448 | luma_addr[1] = luma_addr[0] + 0x40; |
448 | chroma_addr[1] = chroma_addr[0] + 0x40; | 449 | chroma_addr[1] = chroma_addr[0] + 0x40; |
449 | } else { | 450 | } else { |
450 | luma_addr[1] = luma_addr[0] + win_data->fb_width; | 451 | luma_addr[1] = luma_addr[0] + win_data->fb_pitch; |
451 | chroma_addr[1] = chroma_addr[0] + win_data->fb_width; | 452 | chroma_addr[1] = chroma_addr[0] + win_data->fb_pitch; |
452 | } | 453 | } |
453 | } else { | 454 | } else { |
454 | ctx->interlace = false; | 455 | ctx->interlace = false; |
@@ -469,10 +470,10 @@ static void vp_video_buffer(struct mixer_context *ctx, int win) | |||
469 | vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK); | 470 | vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK); |
470 | 471 | ||
471 | /* setting size of input image */ | 472 | /* setting size of input image */ |
472 | vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_width) | | 473 | vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_pitch) | |
473 | VP_IMG_VSIZE(win_data->fb_height)); | 474 | VP_IMG_VSIZE(win_data->fb_height)); |
474 | /* chroma height has to reduced by 2 to avoid chroma distorions */ | 475 | /* chroma height has to reduced by 2 to avoid chroma distorions */ |
475 | vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_width) | | 476 | vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_pitch) | |
476 | VP_IMG_VSIZE(win_data->fb_height / 2)); | 477 | VP_IMG_VSIZE(win_data->fb_height / 2)); |
477 | 478 | ||
478 | vp_reg_write(res, VP_SRC_WIDTH, win_data->src_width); | 479 | vp_reg_write(res, VP_SRC_WIDTH, win_data->src_width); |
@@ -559,7 +560,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) | |||
559 | /* converting dma address base and source offset */ | 560 | /* converting dma address base and source offset */ |
560 | dma_addr = win_data->dma_addr | 561 | dma_addr = win_data->dma_addr |
561 | + (win_data->fb_x * win_data->bpp >> 3) | 562 | + (win_data->fb_x * win_data->bpp >> 3) |
562 | + (win_data->fb_y * win_data->fb_width * win_data->bpp >> 3); | 563 | + (win_data->fb_y * win_data->fb_pitch); |
563 | src_x_offset = 0; | 564 | src_x_offset = 0; |
564 | src_y_offset = 0; | 565 | src_y_offset = 0; |
565 | 566 | ||
@@ -576,7 +577,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) | |||
576 | MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK); | 577 | MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK); |
577 | 578 | ||
578 | /* setup geometry */ | 579 | /* setup geometry */ |
579 | mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width); | 580 | mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), |
581 | win_data->fb_pitch / (win_data->bpp >> 3)); | ||
580 | 582 | ||
581 | /* setup display size */ | 583 | /* setup display size */ |
582 | if (ctx->mxr_ver == MXR_VER_128_0_0_184 && | 584 | if (ctx->mxr_ver == MXR_VER_128_0_0_184 && |
@@ -961,6 +963,7 @@ static void mixer_win_mode_set(struct exynos_drm_crtc *crtc, | |||
961 | win_data->fb_y = plane->fb_y; | 963 | win_data->fb_y = plane->fb_y; |
962 | win_data->fb_width = plane->fb_width; | 964 | win_data->fb_width = plane->fb_width; |
963 | win_data->fb_height = plane->fb_height; | 965 | win_data->fb_height = plane->fb_height; |
966 | win_data->fb_pitch = plane->pitch; | ||
964 | win_data->src_width = plane->src_width; | 967 | win_data->src_width = plane->src_width; |
965 | win_data->src_height = plane->src_height; | 968 | win_data->src_height = plane->src_height; |
966 | 969 | ||
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index b773368fc62c..38a742532c4f 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c | |||
@@ -1487,7 +1487,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |||
1487 | goto err; | 1487 | goto err; |
1488 | } | 1488 | } |
1489 | 1489 | ||
1490 | if (i915_needs_cmd_parser(ring)) { | 1490 | if (i915_needs_cmd_parser(ring) && args->batch_len) { |
1491 | batch_obj = i915_gem_execbuffer_parse(ring, | 1491 | batch_obj = i915_gem_execbuffer_parse(ring, |
1492 | &shadow_exec_entry, | 1492 | &shadow_exec_entry, |
1493 | eb, | 1493 | eb, |
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 0a52c44ad03d..9c5451c97942 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c | |||
@@ -1322,7 +1322,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |||
1322 | drm_modeset_lock_all(dev); | 1322 | drm_modeset_lock_all(dev); |
1323 | 1323 | ||
1324 | plane = drm_plane_find(dev, set->plane_id); | 1324 | plane = drm_plane_find(dev, set->plane_id); |
1325 | if (!plane) { | 1325 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) { |
1326 | ret = -ENOENT; | 1326 | ret = -ENOENT; |
1327 | goto out_unlock; | 1327 | goto out_unlock; |
1328 | } | 1328 | } |
@@ -1349,7 +1349,7 @@ int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |||
1349 | drm_modeset_lock_all(dev); | 1349 | drm_modeset_lock_all(dev); |
1350 | 1350 | ||
1351 | plane = drm_plane_find(dev, get->plane_id); | 1351 | plane = drm_plane_find(dev, get->plane_id); |
1352 | if (!plane) { | 1352 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) { |
1353 | ret = -ENOENT; | 1353 | ret = -ENOENT; |
1354 | goto out_unlock; | 1354 | goto out_unlock; |
1355 | } | 1355 | } |
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index c648e1996dab..243a36c93b8f 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h | |||
@@ -2129,6 +2129,7 @@ | |||
2129 | #define VCE_UENC_REG_CLOCK_GATING 0x207c0 | 2129 | #define VCE_UENC_REG_CLOCK_GATING 0x207c0 |
2130 | #define VCE_SYS_INT_EN 0x21300 | 2130 | #define VCE_SYS_INT_EN 0x21300 |
2131 | # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) | 2131 | # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) |
2132 | #define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c | ||
2132 | #define VCE_LMI_CTRL2 0x21474 | 2133 | #define VCE_LMI_CTRL2 0x21474 |
2133 | #define VCE_LMI_CTRL 0x21498 | 2134 | #define VCE_LMI_CTRL 0x21498 |
2134 | #define VCE_LMI_VM_CTRL 0x214a0 | 2135 | #define VCE_LMI_VM_CTRL 0x214a0 |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 5587603b4a89..33d5a4f4eebd 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -1565,6 +1565,7 @@ struct radeon_dpm { | |||
1565 | int new_active_crtc_count; | 1565 | int new_active_crtc_count; |
1566 | u32 current_active_crtcs; | 1566 | u32 current_active_crtcs; |
1567 | int current_active_crtc_count; | 1567 | int current_active_crtc_count; |
1568 | bool single_display; | ||
1568 | struct radeon_dpm_dynamic_state dyn_state; | 1569 | struct radeon_dpm_dynamic_state dyn_state; |
1569 | struct radeon_dpm_fan fan; | 1570 | struct radeon_dpm_fan fan; |
1570 | u32 tdp_limit; | 1571 | u32 tdp_limit; |
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index 63ccb8fa799c..d27e4ccb848c 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c | |||
@@ -76,7 +76,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev) | |||
76 | 76 | ||
77 | static bool radeon_read_bios(struct radeon_device *rdev) | 77 | static bool radeon_read_bios(struct radeon_device *rdev) |
78 | { | 78 | { |
79 | uint8_t __iomem *bios; | 79 | uint8_t __iomem *bios, val1, val2; |
80 | size_t size; | 80 | size_t size; |
81 | 81 | ||
82 | rdev->bios = NULL; | 82 | rdev->bios = NULL; |
@@ -86,15 +86,19 @@ static bool radeon_read_bios(struct radeon_device *rdev) | |||
86 | return false; | 86 | return false; |
87 | } | 87 | } |
88 | 88 | ||
89 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | 89 | val1 = readb(&bios[0]); |
90 | val2 = readb(&bios[1]); | ||
91 | |||
92 | if (size == 0 || val1 != 0x55 || val2 != 0xaa) { | ||
90 | pci_unmap_rom(rdev->pdev, bios); | 93 | pci_unmap_rom(rdev->pdev, bios); |
91 | return false; | 94 | return false; |
92 | } | 95 | } |
93 | rdev->bios = kmemdup(bios, size, GFP_KERNEL); | 96 | rdev->bios = kzalloc(size, GFP_KERNEL); |
94 | if (rdev->bios == NULL) { | 97 | if (rdev->bios == NULL) { |
95 | pci_unmap_rom(rdev->pdev, bios); | 98 | pci_unmap_rom(rdev->pdev, bios); |
96 | return false; | 99 | return false; |
97 | } | 100 | } |
101 | memcpy_fromio(rdev->bios, bios, size); | ||
98 | pci_unmap_rom(rdev->pdev, bios); | 102 | pci_unmap_rom(rdev->pdev, bios); |
99 | return true; | 103 | return true; |
100 | } | 104 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_mn.c b/drivers/gpu/drm/radeon/radeon_mn.c index a69bd441dd2d..572b4dbec186 100644 --- a/drivers/gpu/drm/radeon/radeon_mn.c +++ b/drivers/gpu/drm/radeon/radeon_mn.c | |||
@@ -122,7 +122,6 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn, | |||
122 | it = interval_tree_iter_first(&rmn->objects, start, end); | 122 | it = interval_tree_iter_first(&rmn->objects, start, end); |
123 | while (it) { | 123 | while (it) { |
124 | struct radeon_bo *bo; | 124 | struct radeon_bo *bo; |
125 | struct fence *fence; | ||
126 | int r; | 125 | int r; |
127 | 126 | ||
128 | bo = container_of(it, struct radeon_bo, mn_it); | 127 | bo = container_of(it, struct radeon_bo, mn_it); |
@@ -134,12 +133,10 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn, | |||
134 | continue; | 133 | continue; |
135 | } | 134 | } |
136 | 135 | ||
137 | fence = reservation_object_get_excl(bo->tbo.resv); | 136 | r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, |
138 | if (fence) { | 137 | false, MAX_SCHEDULE_TIMEOUT); |
139 | r = radeon_fence_wait((struct radeon_fence *)fence, false); | 138 | if (r) |
140 | if (r) | 139 | DRM_ERROR("(%d) failed to wait for user bo\n", r); |
141 | DRM_ERROR("(%d) failed to wait for user bo\n", r); | ||
142 | } | ||
143 | 140 | ||
144 | radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_CPU); | 141 | radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_CPU); |
145 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); | 142 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 33cf4108386d..c1ba83a8dd8c 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c | |||
@@ -837,12 +837,8 @@ static void radeon_dpm_thermal_work_handler(struct work_struct *work) | |||
837 | radeon_pm_compute_clocks(rdev); | 837 | radeon_pm_compute_clocks(rdev); |
838 | } | 838 | } |
839 | 839 | ||
840 | static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, | 840 | static bool radeon_dpm_single_display(struct radeon_device *rdev) |
841 | enum radeon_pm_state_type dpm_state) | ||
842 | { | 841 | { |
843 | int i; | ||
844 | struct radeon_ps *ps; | ||
845 | u32 ui_class; | ||
846 | bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? | 842 | bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? |
847 | true : false; | 843 | true : false; |
848 | 844 | ||
@@ -858,6 +854,17 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, | |||
858 | if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) | 854 | if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) |
859 | single_display = false; | 855 | single_display = false; |
860 | 856 | ||
857 | return single_display; | ||
858 | } | ||
859 | |||
860 | static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, | ||
861 | enum radeon_pm_state_type dpm_state) | ||
862 | { | ||
863 | int i; | ||
864 | struct radeon_ps *ps; | ||
865 | u32 ui_class; | ||
866 | bool single_display = radeon_dpm_single_display(rdev); | ||
867 | |||
861 | /* certain older asics have a separare 3D performance state, | 868 | /* certain older asics have a separare 3D performance state, |
862 | * so try that first if the user selected performance | 869 | * so try that first if the user selected performance |
863 | */ | 870 | */ |
@@ -983,6 +990,7 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) | |||
983 | struct radeon_ps *ps; | 990 | struct radeon_ps *ps; |
984 | enum radeon_pm_state_type dpm_state; | 991 | enum radeon_pm_state_type dpm_state; |
985 | int ret; | 992 | int ret; |
993 | bool single_display = radeon_dpm_single_display(rdev); | ||
986 | 994 | ||
987 | /* if dpm init failed */ | 995 | /* if dpm init failed */ |
988 | if (!rdev->pm.dpm_enabled) | 996 | if (!rdev->pm.dpm_enabled) |
@@ -1007,6 +1015,9 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) | |||
1007 | /* vce just modifies an existing state so force a change */ | 1015 | /* vce just modifies an existing state so force a change */ |
1008 | if (ps->vce_active != rdev->pm.dpm.vce_active) | 1016 | if (ps->vce_active != rdev->pm.dpm.vce_active) |
1009 | goto force; | 1017 | goto force; |
1018 | /* user has made a display change (such as timing) */ | ||
1019 | if (rdev->pm.dpm.single_display != single_display) | ||
1020 | goto force; | ||
1010 | if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { | 1021 | if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { |
1011 | /* for pre-BTC and APUs if the num crtcs changed but state is the same, | 1022 | /* for pre-BTC and APUs if the num crtcs changed but state is the same, |
1012 | * all we need to do is update the display configuration. | 1023 | * all we need to do is update the display configuration. |
@@ -1069,6 +1080,7 @@ force: | |||
1069 | 1080 | ||
1070 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; | 1081 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
1071 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; | 1082 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
1083 | rdev->pm.dpm.single_display = single_display; | ||
1072 | 1084 | ||
1073 | /* wait for the rings to drain */ | 1085 | /* wait for the rings to drain */ |
1074 | for (i = 0; i < RADEON_NUM_RINGS; i++) { | 1086 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 2456f69efd23..8c7872339c2a 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c | |||
@@ -495,7 +495,7 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |||
495 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); | 495 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
496 | seq_printf(m, "%u dwords in ring\n", count); | 496 | seq_printf(m, "%u dwords in ring\n", count); |
497 | 497 | ||
498 | if (!ring->ready) | 498 | if (!ring->ring) |
499 | return 0; | 499 | return 0; |
500 | 500 | ||
501 | /* print 8 dw before current rptr as often it's the last executed | 501 | /* print 8 dw before current rptr as often it's the last executed |
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index d02aa1d0f588..b292aca0f342 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -598,6 +598,10 @@ static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) | |||
598 | enum dma_data_direction direction = write ? | 598 | enum dma_data_direction direction = write ? |
599 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | 599 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; |
600 | 600 | ||
601 | /* double check that we don't free the table twice */ | ||
602 | if (!ttm->sg->sgl) | ||
603 | return; | ||
604 | |||
601 | /* free the sg table and pages again */ | 605 | /* free the sg table and pages again */ |
602 | dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | 606 | dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); |
603 | 607 | ||
diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c index 1ac7bb825a1b..fbbe78fbd087 100644 --- a/drivers/gpu/drm/radeon/vce_v2_0.c +++ b/drivers/gpu/drm/radeon/vce_v2_0.c | |||
@@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev) | |||
156 | WREG32(VCE_LMI_SWAP_CNTL1, 0); | 156 | WREG32(VCE_LMI_SWAP_CNTL1, 0); |
157 | WREG32(VCE_LMI_VM_CTRL, 0); | 157 | WREG32(VCE_LMI_VM_CTRL, 0); |
158 | 158 | ||
159 | WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8); | ||
160 | |||
161 | addr &= 0xff; | ||
159 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); | 162 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); |
160 | WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); | 163 | WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); |
161 | WREG32(VCE_VCPU_CACHE_SIZE0, size); | 164 | WREG32(VCE_VCPU_CACHE_SIZE0, size); |