Merge tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-fixes

drm/tegra: Fixes for v3.20-rc1

This fixes a bit of fallout that was caused by the atomic modesetting
driver conversion and some last-minute changes in the DRM atomic core.
It also fixes a bug exposed by recent changes in the clock framework
which results in non-working HDMI.

* tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux:
  drm/tegra: dc: Move more code into ->init()
  drm/tegra: dc: Wire up CRTC parent of atomic state
  drm/tegra: dc: Reset state's active_changed field
  drm/tegra: hdmi: Explicitly set clock rate

2 files changed, 48 insertions, 39 deletions

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 3aaa84ae2681..1a52522f5da7 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -997,8 +997,10 @@ static void tegra_crtc_reset(struct drm_crtc *crtc)
         crtc->state = NULL;
 
         state = kzalloc(sizeof(*state), GFP_KERNEL);
-        if (state)
+        if (state) {
                 crtc->state = &state->base;
+                crtc->state->crtc = crtc;
+        }
 }
 
 static struct drm_crtc_state *
@@ -1012,6 +1014,7 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
                 return NULL;
 
         copy->base.mode_changed = false;
+        copy->base.active_changed = false;
         copy->base.planes_changed = false;
         copy->base.event = NULL;
 
@@ -1227,9 +1230,6 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
         /* program display mode */
         tegra_dc_set_timings(dc, mode);
 
-        if (dc->soc->supports_border_color)
-                tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
-
         /* interlacing isn't supported yet, so disable it */
         if (dc->soc->supports_interlacing) {
                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
@@ -1252,42 +1252,7 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
 
 static void tegra_crtc_prepare(struct drm_crtc *crtc)
 {
-        struct tegra_dc *dc = to_tegra_dc(crtc);
-        unsigned int syncpt;
-        unsigned long value;
-
         drm_crtc_vblank_off(crtc);
-
-        if (dc->pipe)
-                syncpt = SYNCPT_VBLANK1;
-        else
-                syncpt = SYNCPT_VBLANK0;
-
-        /* initialize display controller */
-        tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
-        tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
-
-        value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
-        tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
-
-        value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
-                WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
-        tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
-
-        /* initialize timer */
-        value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
-                WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
-        tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
-
-        value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
-                WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
-        tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
-
-        value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
-        tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
-
-        value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
-        tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 }
 
 static void tegra_crtc_commit(struct drm_crtc *crtc)
@@ -1664,6 +1629,8 @@ static int tegra_dc_init(struct host1x_client *client)
         struct tegra_drm *tegra = drm->dev_private;
         struct drm_plane *primary = NULL;
         struct drm_plane *cursor = NULL;
+        unsigned int syncpt;
+        u32 value;
         int err;
 
         if (tegra->domain) {
@@ -1730,6 +1697,40 @@ static int tegra_dc_init(struct host1x_client *client)
                 goto cleanup;
         }
 
+        /* initialize display controller */
+        if (dc->pipe)
+                syncpt = SYNCPT_VBLANK1;
+        else
+                syncpt = SYNCPT_VBLANK0;
+
+        tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
+        tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
+
+        value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
+        tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
+
+        value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
+                WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
+        tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
+
+        /* initialize timer */
+        value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
+                WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
+        tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
+
+        value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
+                WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
+        tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
+
+        value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
+        tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
+
+        value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
+        tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
+
+        if (dc->soc->supports_border_color)
+                tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
+
         return 0;
 
 cleanup:
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 7e06657ae58b..7eaaee74a039 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -851,6 +851,14 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
         h_back_porch = mode->htotal - mode->hsync_end;
         h_front_porch = mode->hsync_start - mode->hdisplay;
 
+        err = clk_set_rate(hdmi->clk, pclk);
+        if (err < 0) {
+                dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
+                        err);
+        }
+
+        DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
+
         /* power up sequence */
         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
         value &= ~SOR_PLL_PDBG;