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authorArnd Bergmann <arnd@arndb.de>2013-06-24 10:46:23 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-24 10:46:23 -0400
commit8ecb6ca61ac673f3712f82259de5b0a25d21d532 (patch)
tree8fc2fcf30eb1233e85925be17dcd16a71e522f48
parent3aae7ab0f15d69166789cf84aea39e6b438c4c26 (diff)
parente65abbbc5279319ab679298f8740ddf53e022a5e (diff)
Merge tag 'davinci-for-v3.11/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
From Sekhar Nori: DaVinci SoC updates for v3.11 - part 2 This pull request adds DT and runtime PM to EDMA ARM private API so it can be used on DT enabled DaVinci and OMAP platforms. Also adds DMA channel crossbar mapping support to be used by DT-enabled platforms which use it. * tag 'davinci-for-v3.11/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding ARM: edma: Convert to devm_* api Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--Documentation/devicetree/bindings/dma/ti-edma.txt34
-rw-r--r--arch/arm/common/edma.c329
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c8
-rw-r--r--arch/arm/mach-davinci/devices-tnetv107x.c4
-rw-r--r--arch/arm/mach-davinci/dm355.c4
-rw-r--r--arch/arm/mach-davinci/dm365.c4
-rw-r--r--arch/arm/mach-davinci/dm644x.c4
-rw-r--r--arch/arm/mach-davinci/dm646x.c4
-rw-r--r--arch/arm/mach-omap2/Kconfig1
-rw-r--r--drivers/dma/Kconfig2
-rw-r--r--include/linux/platform_data/edma.h5
11 files changed, 324 insertions, 75 deletions
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
new file mode 100644
index 000000000000..9fbbdb783a72
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -0,0 +1,34 @@
1TI EDMA
2
3Required properties:
4- compatible : "ti,edma3"
5- ti,edma-regions: Number of regions
6- ti,edma-slots: Number of slots
7- #dma-cells: Should be set to <1>
8 Clients should use a single channel number per DMA request.
9- dma-channels: Specify total DMA channels per CC
10- reg: Memory map for accessing module
11- interrupt-parent: Interrupt controller the interrupt is routed through
12- interrupts: Exactly 3 interrupts need to be specified in the order:
13 1. Transfer completion interrupt.
14 2. Memory protection interrupt.
15 3. Error interrupt.
16Optional properties:
17- ti,hwmods: Name of the hwmods associated to the EDMA
18- ti,edma-xbar-event-map: Crossbar event to channel map
19
20Example:
21
22edma: edma@49000000 {
23 reg = <0x49000000 0x10000>;
24 interrupt-parent = <&intc>;
25 interrupts = <12 13 14>;
26 compatible = "ti,edma3";
27 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
28 #dma-cells = <1>;
29 dma-channels = <64>;
30 ti,edma-regions = <4>;
31 ti,edma-slots = <256>;
32 ti,edma-xbar-event-map = <1 12
33 2 13>;
34};
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index a1db6cd8cf79..a432e6c1dac1 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -17,6 +17,7 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 19 */
20#include <linux/err.h>
20#include <linux/kernel.h> 21#include <linux/kernel.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/module.h> 23#include <linux/module.h>
@@ -24,6 +25,13 @@
24#include <linux/platform_device.h> 25#include <linux/platform_device.h>
25#include <linux/io.h> 26#include <linux/io.h>
26#include <linux/slab.h> 27#include <linux/slab.h>
28#include <linux/edma.h>
29#include <linux/err.h>
30#include <linux/of_address.h>
31#include <linux/of_device.h>
32#include <linux/of_dma.h>
33#include <linux/of_irq.h>
34#include <linux/pm_runtime.h>
27 35
28#include <linux/platform_data/edma.h> 36#include <linux/platform_data/edma.h>
29 37
@@ -1368,32 +1376,236 @@ void edma_clear_event(unsigned channel)
1368} 1376}
1369EXPORT_SYMBOL(edma_clear_event); 1377EXPORT_SYMBOL(edma_clear_event);
1370 1378
1371/*-----------------------------------------------------------------------*/ 1379#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1380
1381static int edma_of_read_u32_to_s16_array(const struct device_node *np,
1382 const char *propname, s16 *out_values,
1383 size_t sz)
1384{
1385 int ret;
1386
1387 ret = of_property_read_u16_array(np, propname, out_values, sz);
1388 if (ret)
1389 return ret;
1390
1391 /* Terminate it */
1392 *out_values++ = -1;
1393 *out_values++ = -1;
1394
1395 return 0;
1396}
1397
1398static int edma_xbar_event_map(struct device *dev,
1399 struct device_node *node,
1400 struct edma_soc_info *pdata, int len)
1401{
1402 int ret, i;
1403 struct resource res;
1404 void __iomem *xbar;
1405 const s16 (*xbar_chans)[2];
1406 u32 shift, offset, mux;
1407
1408 xbar_chans = devm_kzalloc(dev,
1409 len/sizeof(s16) + 2*sizeof(s16),
1410 GFP_KERNEL);
1411 if (!xbar_chans)
1412 return -ENOMEM;
1413
1414 ret = of_address_to_resource(node, 1, &res);
1415 if (ret)
1416 return -EIO;
1417
1418 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1419 if (!xbar)
1420 return -ENOMEM;
1421
1422 ret = edma_of_read_u32_to_s16_array(node,
1423 "ti,edma-xbar-event-map",
1424 (s16 *)xbar_chans,
1425 len/sizeof(u32));
1426 if (ret)
1427 return -EIO;
1428
1429 for (i = 0; xbar_chans[i][0] != -1; i++) {
1430 shift = (xbar_chans[i][1] & 0x03) << 3;
1431 offset = xbar_chans[i][1] & 0xfffffffc;
1432 mux = readl(xbar + offset);
1433 mux &= ~(0xff << shift);
1434 mux |= xbar_chans[i][0] << shift;
1435 writel(mux, (xbar + offset));
1436 }
1437
1438 pdata->xbar_chans = xbar_chans;
1439
1440 return 0;
1441}
1442
1443static int edma_of_parse_dt(struct device *dev,
1444 struct device_node *node,
1445 struct edma_soc_info *pdata)
1446{
1447 int ret = 0, i;
1448 u32 value;
1449 struct property *prop;
1450 size_t sz;
1451 struct edma_rsv_info *rsv_info;
1452 s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
1453
1454 memset(pdata, 0, sizeof(struct edma_soc_info));
1455
1456 ret = of_property_read_u32(node, "dma-channels", &value);
1457 if (ret < 0)
1458 return ret;
1459 pdata->n_channel = value;
1460
1461 ret = of_property_read_u32(node, "ti,edma-regions", &value);
1462 if (ret < 0)
1463 return ret;
1464 pdata->n_region = value;
1465
1466 ret = of_property_read_u32(node, "ti,edma-slots", &value);
1467 if (ret < 0)
1468 return ret;
1469 pdata->n_slot = value;
1470
1471 pdata->n_cc = 1;
1472
1473 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1474 if (!rsv_info)
1475 return -ENOMEM;
1476 pdata->rsv = rsv_info;
1477
1478 queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
1479 if (!queue_tc_map)
1480 return -ENOMEM;
1481
1482 for (i = 0; i < 3; i++) {
1483 queue_tc_map[i][0] = i;
1484 queue_tc_map[i][1] = i;
1485 }
1486 queue_tc_map[i][0] = -1;
1487 queue_tc_map[i][1] = -1;
1488
1489 pdata->queue_tc_mapping = queue_tc_map;
1490
1491 queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
1492 if (!queue_priority_map)
1493 return -ENOMEM;
1494
1495 for (i = 0; i < 3; i++) {
1496 queue_priority_map[i][0] = i;
1497 queue_priority_map[i][1] = i;
1498 }
1499 queue_priority_map[i][0] = -1;
1500 queue_priority_map[i][1] = -1;
1501
1502 pdata->queue_priority_mapping = queue_priority_map;
1503
1504 pdata->default_queue = 0;
1505
1506 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1507 if (prop)
1508 ret = edma_xbar_event_map(dev, node, pdata, sz);
1509
1510 return ret;
1511}
1512
1513static struct of_dma_filter_info edma_filter_info = {
1514 .filter_fn = edma_filter_fn,
1515};
1516
1517static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1518 struct device_node *node)
1519{
1520 struct edma_soc_info *info;
1521 int ret;
1522
1523 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1524 if (!info)
1525 return ERR_PTR(-ENOMEM);
1526
1527 ret = edma_of_parse_dt(dev, node, info);
1528 if (ret)
1529 return ERR_PTR(ret);
1530
1531 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1532 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1533 &edma_filter_info);
1372 1534
1373static int __init edma_probe(struct platform_device *pdev) 1535 return info;
1536}
1537#else
1538static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1539 struct device_node *node)
1540{
1541 return ERR_PTR(-ENOSYS);
1542}
1543#endif
1544
1545static int edma_probe(struct platform_device *pdev)
1374{ 1546{
1375 struct edma_soc_info **info = pdev->dev.platform_data; 1547 struct edma_soc_info **info = pdev->dev.platform_data;
1376 const s8 (*queue_priority_mapping)[2]; 1548 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1377 const s8 (*queue_tc_mapping)[2]; 1549 s8 (*queue_priority_mapping)[2];
1550 s8 (*queue_tc_mapping)[2];
1378 int i, j, off, ln, found = 0; 1551 int i, j, off, ln, found = 0;
1379 int status = -1; 1552 int status = -1;
1380 const s16 (*rsv_chans)[2]; 1553 const s16 (*rsv_chans)[2];
1381 const s16 (*rsv_slots)[2]; 1554 const s16 (*rsv_slots)[2];
1555 const s16 (*xbar_chans)[2];
1382 int irq[EDMA_MAX_CC] = {0, 0}; 1556 int irq[EDMA_MAX_CC] = {0, 0};
1383 int err_irq[EDMA_MAX_CC] = {0, 0}; 1557 int err_irq[EDMA_MAX_CC] = {0, 0};
1384 struct resource *r[EDMA_MAX_CC] = {NULL}; 1558 struct resource *r[EDMA_MAX_CC] = {NULL};
1385 resource_size_t len[EDMA_MAX_CC]; 1559 struct resource res[EDMA_MAX_CC];
1386 char res_name[10]; 1560 char res_name[10];
1387 char irq_name[10]; 1561 char irq_name[10];
1562 struct device_node *node = pdev->dev.of_node;
1563 struct device *dev = &pdev->dev;
1564 int ret;
1565
1566 if (node) {
1567 /* Check if this is a second instance registered */
1568 if (arch_num_cc) {
1569 dev_err(dev, "only one EDMA instance is supported via DT\n");
1570 return -ENODEV;
1571 }
1572
1573 ninfo[0] = edma_setup_info_from_dt(dev, node);
1574 if (IS_ERR(ninfo[0])) {
1575 dev_err(dev, "failed to get DT data\n");
1576 return PTR_ERR(ninfo[0]);
1577 }
1578
1579 info = ninfo;
1580 }
1388 1581
1389 if (!info) 1582 if (!info)
1390 return -ENODEV; 1583 return -ENODEV;
1391 1584
1585 pm_runtime_enable(dev);
1586 ret = pm_runtime_get_sync(dev);
1587 if (ret < 0) {
1588 dev_err(dev, "pm_runtime_get_sync() failed\n");
1589 return ret;
1590 }
1591
1392 for (j = 0; j < EDMA_MAX_CC; j++) { 1592 for (j = 0; j < EDMA_MAX_CC; j++) {
1393 sprintf(res_name, "edma_cc%d", j); 1593 if (!info[j]) {
1394 r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1594 if (!found)
1595 return -ENODEV;
1596 break;
1597 }
1598 if (node) {
1599 ret = of_address_to_resource(node, j, &res[j]);
1600 if (!ret)
1601 r[j] = &res[j];
1602 } else {
1603 sprintf(res_name, "edma_cc%d", j);
1604 r[j] = platform_get_resource_byname(pdev,
1605 IORESOURCE_MEM,
1395 res_name); 1606 res_name);
1396 if (!r[j] || !info[j]) { 1607 }
1608 if (!r[j]) {
1397 if (found) 1609 if (found)
1398 break; 1610 break;
1399 else 1611 else
@@ -1402,26 +1614,14 @@ static int __init edma_probe(struct platform_device *pdev)
1402 found = 1; 1614 found = 1;
1403 } 1615 }
1404 1616
1405 len[j] = resource_size(r[j]); 1617 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1618 if (IS_ERR(edmacc_regs_base[j]))
1619 return PTR_ERR(edmacc_regs_base[j]);
1406 1620
1407 r[j] = request_mem_region(r[j]->start, len[j], 1621 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1408 dev_name(&pdev->dev)); 1622 GFP_KERNEL);
1409 if (!r[j]) { 1623 if (!edma_cc[j])
1410 status = -EBUSY; 1624 return -ENOMEM;
1411 goto fail1;
1412 }
1413
1414 edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
1415 if (!edmacc_regs_base[j]) {
1416 status = -EBUSY;
1417 goto fail1;
1418 }
1419
1420 edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
1421 if (!edma_cc[j]) {
1422 status = -ENOMEM;
1423 goto fail1;
1424 }
1425 1625
1426 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, 1626 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
1427 EDMA_MAX_DMACH); 1627 EDMA_MAX_DMACH);
@@ -1452,7 +1652,7 @@ static int __init edma_probe(struct platform_device *pdev)
1452 off = rsv_chans[i][0]; 1652 off = rsv_chans[i][0];
1453 ln = rsv_chans[i][1]; 1653 ln = rsv_chans[i][1];
1454 clear_bits(off, ln, 1654 clear_bits(off, ln,
1455 edma_cc[j]->edma_unused); 1655 edma_cc[j]->edma_unused);
1456 } 1656 }
1457 } 1657 }
1458 1658
@@ -1468,26 +1668,48 @@ static int __init edma_probe(struct platform_device *pdev)
1468 } 1668 }
1469 } 1669 }
1470 1670
1471 sprintf(irq_name, "edma%d", j); 1671 /* Clear the xbar mapped channels in unused list */
1472 irq[j] = platform_get_irq_byname(pdev, irq_name); 1672 xbar_chans = info[j]->xbar_chans;
1673 if (xbar_chans) {
1674 for (i = 0; xbar_chans[i][1] != -1; i++) {
1675 off = xbar_chans[i][1];
1676 clear_bits(off, 1,
1677 edma_cc[j]->edma_unused);
1678 }
1679 }
1680
1681 if (node) {
1682 irq[j] = irq_of_parse_and_map(node, 0);
1683 } else {
1684 sprintf(irq_name, "edma%d", j);
1685 irq[j] = platform_get_irq_byname(pdev, irq_name);
1686 }
1473 edma_cc[j]->irq_res_start = irq[j]; 1687 edma_cc[j]->irq_res_start = irq[j];
1474 status = request_irq(irq[j], dma_irq_handler, 0, "edma", 1688 status = devm_request_irq(&pdev->dev, irq[j],
1475 &pdev->dev); 1689 dma_irq_handler, 0, "edma",
1690 &pdev->dev);
1476 if (status < 0) { 1691 if (status < 0) {
1477 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", 1692 dev_dbg(&pdev->dev,
1693 "devm_request_irq %d failed --> %d\n",
1478 irq[j], status); 1694 irq[j], status);
1479 goto fail; 1695 return status;
1480 } 1696 }
1481 1697
1482 sprintf(irq_name, "edma%d_err", j); 1698 if (node) {
1483 err_irq[j] = platform_get_irq_byname(pdev, irq_name); 1699 err_irq[j] = irq_of_parse_and_map(node, 2);
1700 } else {
1701 sprintf(irq_name, "edma%d_err", j);
1702 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1703 }
1484 edma_cc[j]->irq_res_end = err_irq[j]; 1704 edma_cc[j]->irq_res_end = err_irq[j];
1485 status = request_irq(err_irq[j], dma_ccerr_handler, 0, 1705 status = devm_request_irq(&pdev->dev, err_irq[j],
1486 "edma_error", &pdev->dev); 1706 dma_ccerr_handler, 0,
1707 "edma_error", &pdev->dev);
1487 if (status < 0) { 1708 if (status < 0) {
1488 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", 1709 dev_dbg(&pdev->dev,
1710 "devm_request_irq %d failed --> %d\n",
1489 err_irq[j], status); 1711 err_irq[j], status);
1490 goto fail; 1712 return status;
1491 } 1713 }
1492 1714
1493 for (i = 0; i < edma_cc[j]->num_channels; i++) 1715 for (i = 0; i < edma_cc[j]->num_channels; i++)
@@ -1522,28 +1744,19 @@ static int __init edma_probe(struct platform_device *pdev)
1522 } 1744 }
1523 1745
1524 return 0; 1746 return 0;
1525
1526fail:
1527 for (i = 0; i < EDMA_MAX_CC; i++) {
1528 if (err_irq[i])
1529 free_irq(err_irq[i], &pdev->dev);
1530 if (irq[i])
1531 free_irq(irq[i], &pdev->dev);
1532 }
1533fail1:
1534 for (i = 0; i < EDMA_MAX_CC; i++) {
1535 if (r[i])
1536 release_mem_region(r[i]->start, len[i]);
1537 if (edmacc_regs_base[i])
1538 iounmap(edmacc_regs_base[i]);
1539 kfree(edma_cc[i]);
1540 }
1541 return status;
1542} 1747}
1543 1748
1749static const struct of_device_id edma_of_ids[] = {
1750 { .compatible = "ti,edma3", },
1751 {}
1752};
1544 1753
1545static struct platform_driver edma_driver = { 1754static struct platform_driver edma_driver = {
1546 .driver.name = "edma", 1755 .driver = {
1756 .name = "edma",
1757 .of_match_table = edma_of_ids,
1758 },
1759 .probe = edma_probe,
1547}; 1760};
1548 1761
1549static int __init edma_init(void) 1762static int __init edma_init(void)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf572525175d..eb254fe861ac 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -105,27 +105,27 @@ struct platform_device da8xx_serial_device = {
105 }, 105 },
106}; 106};
107 107
108static const s8 da8xx_queue_tc_mapping[][2] = { 108static s8 da8xx_queue_tc_mapping[][2] = {
109 /* {event queue no, TC no} */ 109 /* {event queue no, TC no} */
110 {0, 0}, 110 {0, 0},
111 {1, 1}, 111 {1, 1},
112 {-1, -1} 112 {-1, -1}
113}; 113};
114 114
115static const s8 da8xx_queue_priority_mapping[][2] = { 115static s8 da8xx_queue_priority_mapping[][2] = {
116 /* {event queue no, Priority} */ 116 /* {event queue no, Priority} */
117 {0, 3}, 117 {0, 3},
118 {1, 7}, 118 {1, 7},
119 {-1, -1} 119 {-1, -1}
120}; 120};
121 121
122static const s8 da850_queue_tc_mapping[][2] = { 122static s8 da850_queue_tc_mapping[][2] = {
123 /* {event queue no, TC no} */ 123 /* {event queue no, TC no} */
124 {0, 0}, 124 {0, 0},
125 {-1, -1} 125 {-1, -1}
126}; 126};
127 127
128static const s8 da850_queue_priority_mapping[][2] = { 128static s8 da850_queue_priority_mapping[][2] = {
129 /* {event queue no, Priority} */ 129 /* {event queue no, Priority} */
130 {0, 3}, 130 {0, 3},
131 {-1, -1} 131 {-1, -1}
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 612a0856e9c5..128cb9ae80f4 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -58,14 +58,14 @@
58#define TNETV107X_DMACH_SDIO1_RX 28 58#define TNETV107X_DMACH_SDIO1_RX 28
59#define TNETV107X_DMACH_SDIO1_TX 29 59#define TNETV107X_DMACH_SDIO1_TX 29
60 60
61static const s8 edma_tc_mapping[][2] = { 61static s8 edma_tc_mapping[][2] = {
62 /* event queue no TC no */ 62 /* event queue no TC no */
63 { 0, 0 }, 63 { 0, 0 },
64 { 1, 1 }, 64 { 1, 1 },
65 { -1, -1 } 65 { -1, -1 }
66}; 66};
67 67
68static const s8 edma_priority_mapping[][2] = { 68static s8 edma_priority_mapping[][2] = {
69 /* event queue no Prio */ 69 /* event queue no Prio */
70 { 0, 3 }, 70 { 0, 3 },
71 { 1, 7 }, 71 { 1, 7 },
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 526cf7d06d0e..42ef53f62c6c 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -569,7 +569,7 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
569 569
570/*----------------------------------------------------------------------*/ 570/*----------------------------------------------------------------------*/
571 571
572static const s8 572static s8
573queue_tc_mapping[][2] = { 573queue_tc_mapping[][2] = {
574 /* {event queue no, TC no} */ 574 /* {event queue no, TC no} */
575 {0, 0}, 575 {0, 0},
@@ -577,7 +577,7 @@ queue_tc_mapping[][2] = {
577 {-1, -1}, 577 {-1, -1},
578}; 578};
579 579
580static const s8 580static s8
581queue_priority_mapping[][2] = { 581queue_priority_mapping[][2] = {
582 /* {event queue no, Priority} */ 582 /* {event queue no, Priority} */
583 {0, 3}, 583 {0, 3},
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index c4b741173c06..fa7af5eda52d 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -826,7 +826,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
826}; 826};
827 827
828/* Four Transfer Controllers on DM365 */ 828/* Four Transfer Controllers on DM365 */
829static const s8 829static s8
830dm365_queue_tc_mapping[][2] = { 830dm365_queue_tc_mapping[][2] = {
831 /* {event queue no, TC no} */ 831 /* {event queue no, TC no} */
832 {0, 0}, 832 {0, 0},
@@ -836,7 +836,7 @@ dm365_queue_tc_mapping[][2] = {
836 {-1, -1}, 836 {-1, -1},
837}; 837};
838 838
839static const s8 839static s8
840dm365_queue_priority_mapping[][2] = { 840dm365_queue_priority_mapping[][2] = {
841 /* {event queue no, Priority} */ 841 /* {event queue no, Priority} */
842 {0, 7}, 842 {0, 7},
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index dd156d58fe64..a49d18246fe9 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -497,7 +497,7 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
497 497
498/*----------------------------------------------------------------------*/ 498/*----------------------------------------------------------------------*/
499 499
500static const s8 500static s8
501queue_tc_mapping[][2] = { 501queue_tc_mapping[][2] = {
502 /* {event queue no, TC no} */ 502 /* {event queue no, TC no} */
503 {0, 0}, 503 {0, 0},
@@ -505,7 +505,7 @@ queue_tc_mapping[][2] = {
505 {-1, -1}, 505 {-1, -1},
506}; 506};
507 507
508static const s8 508static s8
509queue_priority_mapping[][2] = { 509queue_priority_mapping[][2] = {
510 /* {event queue no, Priority} */ 510 /* {event queue no, Priority} */
511 {0, 3}, 511 {0, 3},
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 6d52a321a8cf..d1259e80141b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -531,7 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
531/*----------------------------------------------------------------------*/ 531/*----------------------------------------------------------------------*/
532 532
533/* Four Transfer Controllers on DM646x */ 533/* Four Transfer Controllers on DM646x */
534static const s8 534static s8
535dm646x_queue_tc_mapping[][2] = { 535dm646x_queue_tc_mapping[][2] = {
536 /* {event queue no, TC no} */ 536 /* {event queue no, TC no} */
537 {0, 0}, 537 {0, 0},
@@ -541,7 +541,7 @@ dm646x_queue_tc_mapping[][2] = {
541 {-1, -1}, 541 {-1, -1},
542}; 542};
543 543
544static const s8 544static s8
545dm646x_queue_priority_mapping[][2] = { 545dm646x_queue_priority_mapping[][2] = {
546 /* {event queue no, Priority} */ 546 /* {event queue no, Priority} */
547 {0, 4}, 547 {0, 4},
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1bfe9ee0331b..a5679a68cd35 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -17,6 +17,7 @@ config ARCH_OMAP2PLUS
17 select PROC_DEVICETREE if PROC_FS 17 select PROC_DEVICETREE if PROC_FS
18 select SOC_BUS 18 select SOC_BUS
19 select SPARSE_IRQ 19 select SPARSE_IRQ
20 select TI_PRIV_EDMA
20 select USE_OF 21 select USE_OF
21 help 22 help
22 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 23 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index e9924898043a..3215a3cb3de8 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -213,7 +213,7 @@ config SIRF_DMA
213 213
214config TI_EDMA 214config TI_EDMA
215 tristate "TI EDMA support" 215 tristate "TI EDMA support"
216 depends on ARCH_DAVINCI 216 depends on ARCH_DAVINCI || ARCH_OMAP
217 select DMA_ENGINE 217 select DMA_ENGINE
218 select DMA_VIRTUAL_CHANNELS 218 select DMA_VIRTUAL_CHANNELS
219 default n 219 default n
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index 2344ea2675ad..57300fd7cc03 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -175,8 +175,9 @@ struct edma_soc_info {
175 /* Resource reservation for other cores */ 175 /* Resource reservation for other cores */
176 struct edma_rsv_info *rsv; 176 struct edma_rsv_info *rsv;
177 177
178 const s8 (*queue_tc_mapping)[2]; 178 s8 (*queue_tc_mapping)[2];
179 const s8 (*queue_priority_mapping)[2]; 179 s8 (*queue_priority_mapping)[2];
180 const s16 (*xbar_chans)[2];
180}; 181};
181 182
182#endif 183#endif