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authorYijing Wang <wangyijing@huawei.com>2014-11-11 17:45:31 -0500
committerBjorn Helgaas <bhelgaas@google.com>2014-11-21 11:34:23 -0500
commit8dd26dc8fecab05aa92cd7f109f691c1283c5a13 (patch)
tree973359f6203f47b4bb19f533d228bcea9e935b50
parent26914233b1cc290f7b5c0189f7d121ad345df48b (diff)
PCI: xilinx: Save MSI controller in pci_sys_data
Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use xilinx_pcie_msi_chip, not xilinx_pcie_msi_controller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/host/pcie-xilinx.c20
1 files changed, 5 insertions, 15 deletions
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f41bc601b7b0..eca292347c69 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -432,20 +432,6 @@ static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
432 pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2); 432 pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
433} 433}
434 434
435/**
436 * xilinx_pcie_add_bus - Add MSI chip info to PCIe bus
437 * @bus: PCIe bus
438 */
439static void xilinx_pcie_add_bus(struct pci_bus *bus)
440{
441 if (IS_ENABLED(CONFIG_PCI_MSI)) {
442 struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
443
444 xilinx_pcie_msi_chip.dev = port->dev;
445 bus->msi = &xilinx_pcie_msi_chip;
446 }
447}
448
449/* INTx Functions */ 435/* INTx Functions */
450 436
451/** 437/**
@@ -925,10 +911,14 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
925 .private_data = (void **)&port, 911 .private_data = (void **)&port,
926 .setup = xilinx_pcie_setup, 912 .setup = xilinx_pcie_setup,
927 .map_irq = of_irq_parse_and_map_pci, 913 .map_irq = of_irq_parse_and_map_pci,
928 .add_bus = xilinx_pcie_add_bus,
929 .scan = xilinx_pcie_scan_bus, 914 .scan = xilinx_pcie_scan_bus,
930 .ops = &xilinx_pcie_ops, 915 .ops = &xilinx_pcie_ops,
931 }; 916 };
917
918#ifdef CONFIG_PCI_MSI
919 xilinx_pcie_msi_chip.dev = port->dev;
920 hw.msi_ctrl = &xilinx_pcie_msi_chip;
921#endif
932 pci_common_init_dev(dev, &hw); 922 pci_common_init_dev(dev, &hw);
933 923
934 return 0; 924 return 0;