diff options
author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2014-03-14 10:19:08 -0400 |
---|---|---|
committer | Thierry Reding <thierry.reding@gmail.com> | 2014-03-18 15:47:31 -0400 |
commit | 8db9e29fe540c9640ea60f37ecf99d3a73bd12c5 (patch) | |
tree | d7458bb791e71432ad12fe47aa9380d78830733f | |
parent | 42586315b7b6e682bd4136a1a2bc2b1d50113487 (diff) |
pwm: atmel: Fix polarity handling
When atmel_pwm_config() calculates and then sets the prescaler, it is
overwriting the channel's CMR register so we are losing the CPOL
configuration.
As atmel_pwm_config() is always called before enabling a channel,
inverting the polarity doesn't work.
Fix that by reading CMR first and only overwriting the prescaler bits.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
-rw-r--r-- | drivers/pwm/pwm-atmel.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index bf4144a14661..2d69e9c431dd 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c | |||
@@ -32,6 +32,7 @@ | |||
32 | /* Bit field in CMR */ | 32 | /* Bit field in CMR */ |
33 | #define PWM_CMR_CPOL (1 << 9) | 33 | #define PWM_CMR_CPOL (1 << 9) |
34 | #define PWM_CMR_UPD_CDTY (1 << 10) | 34 | #define PWM_CMR_UPD_CDTY (1 << 10) |
35 | #define PWM_CMR_CPRE_MSK 0xF | ||
35 | 36 | ||
36 | /* The following registers for PWM v1 */ | 37 | /* The following registers for PWM v1 */ |
37 | #define PWMV1_CDTY 0x04 | 38 | #define PWMV1_CDTY 0x04 |
@@ -104,6 +105,7 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |||
104 | unsigned long clk_rate, prd, dty; | 105 | unsigned long clk_rate, prd, dty; |
105 | unsigned long long div; | 106 | unsigned long long div; |
106 | unsigned int pres = 0; | 107 | unsigned int pres = 0; |
108 | u32 val; | ||
107 | int ret; | 109 | int ret; |
108 | 110 | ||
109 | if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) { | 111 | if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) { |
@@ -139,7 +141,10 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |||
139 | return ret; | 141 | return ret; |
140 | } | 142 | } |
141 | 143 | ||
142 | atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, pres); | 144 | /* It is necessary to preserve CPOL, inside CMR */ |
145 | val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); | ||
146 | val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); | ||
147 | atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); | ||
143 | atmel_pwm->config(chip, pwm, dty, prd); | 148 | atmel_pwm->config(chip, pwm, dty, prd); |
144 | 149 | ||
145 | clk_disable(atmel_pwm->clk); | 150 | clk_disable(atmel_pwm->clk); |