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authorLinus Torvalds <torvalds@linux-foundation.org>2015-01-26 17:51:19 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-01-26 17:51:19 -0500
commit8d6b9327cb6a6d50f9b9719f99b52352568f5c08 (patch)
treefb31898af58fba85f4f42f0dfe81289342951622
parent26bc420b59a38e4e6685a73345a0def461136dce (diff)
parent06a5687f82bd7f1fbf56363351c47e8c337302fc (diff)
Merge tag 'spi-v3.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown: "A few driver specific fixes here, some fixes for issues introduced and discovered during recent work on the DesignWare driver (which has been getting a lot of attention recently) and a couple of other drivers. All serious things for people who run into them" * tag 'spi-v3.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: dw: amend warning message spi: sh-msiof: fix MDR1_FLD_MASK value spi: dw-mid: fix FIFO size spi: dw: Fix detecting FIFO depth spi/pxa2xx: Clear cur_chip pointer before starting next message
-rw-r--r--drivers/spi/spi-dw-mid.c1
-rw-r--r--drivers/spi/spi-dw.c6
-rw-r--r--drivers/spi/spi-pxa2xx.c2
-rw-r--r--drivers/spi/spi-sh-msiof.c2
4 files changed, 5 insertions, 6 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 7281316a5ecb..a67d37c7e3c0 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -271,7 +271,6 @@ int dw_spi_mid_init(struct dw_spi *dws)
271 iounmap(clk_reg); 271 iounmap(clk_reg);
272 272
273 dws->num_cs = 16; 273 dws->num_cs = 16;
274 dws->fifo_len = 40; /* FIFO has 40 words buffer */
275 274
276#ifdef CONFIG_SPI_DW_MID_DMA 275#ifdef CONFIG_SPI_DW_MID_DMA
277 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL); 276 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index d0d5542efc06..8edcd1b84562 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -621,13 +621,13 @@ static void spi_hw_init(struct dw_spi *dws)
621 if (!dws->fifo_len) { 621 if (!dws->fifo_len) {
622 u32 fifo; 622 u32 fifo;
623 623
624 for (fifo = 2; fifo <= 257; fifo++) { 624 for (fifo = 2; fifo <= 256; fifo++) {
625 dw_writew(dws, DW_SPI_TXFLTR, fifo); 625 dw_writew(dws, DW_SPI_TXFLTR, fifo);
626 if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) 626 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
627 break; 627 break;
628 } 628 }
629 629
630 dws->fifo_len = (fifo == 257) ? 0 : fifo; 630 dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;
631 dw_writew(dws, DW_SPI_TXFLTR, 0); 631 dw_writew(dws, DW_SPI_TXFLTR, 0);
632 } 632 }
633} 633}
@@ -673,7 +673,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
673 if (dws->dma_ops && dws->dma_ops->dma_init) { 673 if (dws->dma_ops && dws->dma_ops->dma_init) {
674 ret = dws->dma_ops->dma_init(dws); 674 ret = dws->dma_ops->dma_init(dws);
675 if (ret) { 675 if (ret) {
676 dev_warn(&master->dev, "DMA init failed\n"); 676 dev_warn(dev, "DMA init failed\n");
677 dws->dma_inited = 0; 677 dws->dma_inited = 0;
678 } 678 }
679 } 679 }
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 05c623cfb078..23822e7df6c1 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -546,8 +546,8 @@ static void giveback(struct driver_data *drv_data)
546 cs_deassert(drv_data); 546 cs_deassert(drv_data);
547 } 547 }
548 548
549 spi_finalize_current_message(drv_data->master);
550 drv_data->cur_chip = NULL; 549 drv_data->cur_chip = NULL;
550 spi_finalize_current_message(drv_data->master);
551} 551}
552 552
553static void reset_sccr1(struct driver_data *drv_data) 553static void reset_sccr1(struct driver_data *drv_data)
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 96a5fc0878d8..3ab7a21445fc 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -82,7 +82,7 @@ struct sh_msiof_spi_priv {
82#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ 82#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
83#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 83#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
84#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 84#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
85#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ 85#define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
86#define MDR1_FLD_SHIFT 2 86#define MDR1_FLD_SHIFT 2
87#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ 87#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
88/* TMDR1 */ 88/* TMDR1 */