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authorStephen Warren <swarren@nvidia.com>2015-02-24 16:00:48 -0500
committerLinus Walleij <linus.walleij@linaro.org>2015-03-09 13:10:57 -0400
commit8d4684b39b5865ef5471a256adfcd8d7c3e18d43 (patch)
tree736e56c1c3b1cd0f1d59c0e300fdf380788ffd74
parentb5eec4d061cad4a084c05c7dadd6884fd5fe0df9 (diff)
pinctrl: tegra: driver layout/consistency fixes
Various non-semantic tweaks and layout/consistency fixes for existing Tegra pinctrl drivers. Move the definition of DRV_PINGROUP_REG() before the definition of PINGROUP() so that a future SoC driver can invoke the former from the latter. PINGROUP_BIT_Y(n) is just n, so replace it with n. Re-wrap the parameters to *PINGROUP(). Keep various enums sorted in the Tegra124 driver. Various white-space consistency fixes. These changes aim to update existing drivers to be consistent with future SoC drivers. While we could ignore these tweaks to the existing drivers, I'd like to keep everything as consistent as possible for easy comparison. Besides, I auto-generate the drivers, and maintaining special-cases to keep the differences in place is annoying. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c14
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c29
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c113
3 files changed, 75 insertions, 81 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 52e4ec6386b4..0740cdba7508 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1547,6 +1547,7 @@ static struct tegra_function tegra114_functions[] = {
1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1548#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1548#define PINGROUP_REG_A 0x3000 /* bank 1 */
1549 1549
1550#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1550#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 1551#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1551 1552
1552#define PINGROUP_BIT_Y(b) (b) 1553#define PINGROUP_BIT_Y(b) (b)
@@ -1572,20 +1573,17 @@ static struct tegra_function tegra114_functions[] = {
1572 .tri_reg = PINGROUP_REG(r), \ 1573 .tri_reg = PINGROUP_REG(r), \
1573 .tri_bank = 1, \ 1574 .tri_bank = 1, \
1574 .tri_bit = 4, \ 1575 .tri_bit = 4, \
1575 .einput_bit = PINGROUP_BIT_Y(5), \ 1576 .einput_bit = 5, \
1576 .odrain_bit = PINGROUP_BIT_##od(6), \ 1577 .odrain_bit = PINGROUP_BIT_##od(6), \
1577 .lock_bit = PINGROUP_BIT_Y(7), \ 1578 .lock_bit = 7, \
1578 .ioreset_bit = PINGROUP_BIT_##ior(8), \ 1579 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1579 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ 1580 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1580 .drv_reg = -1, \ 1581 .drv_reg = -1, \
1581 } 1582 }
1582 1583
1583#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) 1584#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
1584 1585 drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
1585#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1586 slwf_b, slwf_w, drvtype) \
1586 drvdn_b, drvdn_w, drvup_b, drvup_w, \
1587 slwr_b, slwr_w, slwf_b, slwf_w, \
1588 drvtype) \
1589 { \ 1587 { \
1590 .name = "drive_" #pg_name, \ 1588 .name = "drive_" #pg_name, \
1591 .pins = drive_##pg_name##_pins, \ 1589 .pins = drive_##pg_name##_pins, \
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index 2b20906c5356..b7ba26064dbf 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -1536,6 +1536,7 @@ enum tegra_mux {
1536 TEGRA_MUX_CLK, 1536 TEGRA_MUX_CLK,
1537 TEGRA_MUX_CLK12, 1537 TEGRA_MUX_CLK12,
1538 TEGRA_MUX_CPU, 1538 TEGRA_MUX_CPU,
1539 TEGRA_MUX_CSI,
1539 TEGRA_MUX_DAP, 1540 TEGRA_MUX_DAP,
1540 TEGRA_MUX_DAP1, 1541 TEGRA_MUX_DAP1,
1541 TEGRA_MUX_DAP2, 1542 TEGRA_MUX_DAP2,
@@ -1544,6 +1545,7 @@ enum tegra_mux {
1544 TEGRA_MUX_DISPLAYA_ALT, 1545 TEGRA_MUX_DISPLAYA_ALT,
1545 TEGRA_MUX_DISPLAYB, 1546 TEGRA_MUX_DISPLAYB,
1546 TEGRA_MUX_DP, 1547 TEGRA_MUX_DP,
1548 TEGRA_MUX_DSI_B,
1547 TEGRA_MUX_DTV, 1549 TEGRA_MUX_DTV,
1548 TEGRA_MUX_EXTPERIPH1, 1550 TEGRA_MUX_EXTPERIPH1,
1549 TEGRA_MUX_EXTPERIPH2, 1551 TEGRA_MUX_EXTPERIPH2,
@@ -1613,8 +1615,6 @@ enum tegra_mux {
1613 TEGRA_MUX_VI_ALT3, 1615 TEGRA_MUX_VI_ALT3,
1614 TEGRA_MUX_VIMCLK2, 1616 TEGRA_MUX_VIMCLK2,
1615 TEGRA_MUX_VIMCLK2_ALT, 1617 TEGRA_MUX_VIMCLK2_ALT,
1616 TEGRA_MUX_CSI,
1617 TEGRA_MUX_DSI_B,
1618}; 1618};
1619 1619
1620#define FUNCTION(fname) \ 1620#define FUNCTION(fname) \
@@ -1630,6 +1630,7 @@ static struct tegra_function tegra124_functions[] = {
1630 FUNCTION(clk), 1630 FUNCTION(clk),
1631 FUNCTION(clk12), 1631 FUNCTION(clk12),
1632 FUNCTION(cpu), 1632 FUNCTION(cpu),
1633 FUNCTION(csi),
1633 FUNCTION(dap), 1634 FUNCTION(dap),
1634 FUNCTION(dap1), 1635 FUNCTION(dap1),
1635 FUNCTION(dap2), 1636 FUNCTION(dap2),
@@ -1638,6 +1639,7 @@ static struct tegra_function tegra124_functions[] = {
1638 FUNCTION(displaya_alt), 1639 FUNCTION(displaya_alt),
1639 FUNCTION(displayb), 1640 FUNCTION(displayb),
1640 FUNCTION(dp), 1641 FUNCTION(dp),
1642 FUNCTION(dsi_b),
1641 FUNCTION(dtv), 1643 FUNCTION(dtv),
1642 FUNCTION(extperiph1), 1644 FUNCTION(extperiph1),
1643 FUNCTION(extperiph2), 1645 FUNCTION(extperiph2),
@@ -1707,15 +1709,15 @@ static struct tegra_function tegra124_functions[] = {
1707 FUNCTION(vi_alt3), 1709 FUNCTION(vi_alt3),
1708 FUNCTION(vimclk2), 1710 FUNCTION(vimclk2),
1709 FUNCTION(vimclk2_alt), 1711 FUNCTION(vimclk2_alt),
1710 FUNCTION(csi),
1711 FUNCTION(dsi_b),
1712}; 1712};
1713 1713
1714#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1714#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1715#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1715#define PINGROUP_REG_A 0x3000 /* bank 1 */
1716#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */ 1716#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
1717 1717
1718#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1718#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 1719#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1720#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1719 1721
1720#define PINGROUP_BIT_Y(b) (b) 1722#define PINGROUP_BIT_Y(b) (b)
1721#define PINGROUP_BIT_N(b) (-1) 1723#define PINGROUP_BIT_N(b) (-1)
@@ -1740,20 +1742,17 @@ static struct tegra_function tegra124_functions[] = {
1740 .tri_reg = PINGROUP_REG(r), \ 1742 .tri_reg = PINGROUP_REG(r), \
1741 .tri_bank = 1, \ 1743 .tri_bank = 1, \
1742 .tri_bit = 4, \ 1744 .tri_bit = 4, \
1743 .einput_bit = PINGROUP_BIT_Y(5), \ 1745 .einput_bit = 5, \
1744 .odrain_bit = PINGROUP_BIT_##od(6), \ 1746 .odrain_bit = PINGROUP_BIT_##od(6), \
1745 .lock_bit = PINGROUP_BIT_Y(7), \ 1747 .lock_bit = 7, \
1746 .ioreset_bit = PINGROUP_BIT_##ior(8), \ 1748 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1747 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ 1749 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1748 .drv_reg = -1, \ 1750 .drv_reg = -1, \
1749 } 1751 }
1750 1752
1751#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) 1753#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
1752 1754 drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
1753#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1755 slwf_b, slwf_w, drvtype) \
1754 drvdn_b, drvdn_w, drvup_b, drvup_w, \
1755 slwr_b, slwr_w, slwf_b, slwf_w, \
1756 drvtype) \
1757 { \ 1756 { \
1758 .name = "drive_" #pg_name, \ 1757 .name = "drive_" #pg_name, \
1759 .pins = drive_##pg_name##_pins, \ 1758 .pins = drive_##pg_name##_pins, \
@@ -1782,8 +1781,6 @@ static struct tegra_function tegra124_functions[] = {
1782 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ 1781 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1783 } 1782 }
1784 1783
1785#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1786
1787#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \ 1784#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
1788 { \ 1785 { \
1789 .name = "mipi_pad_ctrl_" #pg_name, \ 1786 .name = "mipi_pad_ctrl_" #pg_name, \
@@ -2044,8 +2041,8 @@ static const struct tegra_pingroup tegra124_groups[] = {
2044 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 2041 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2045 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 2042 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2046 2043
2047 /* pg_name, r b f0, f1 */ 2044 /* pg_name, r, b, f0, f1 */
2048 MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B) 2045 MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B),
2049}; 2046};
2050 2047
2051static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { 2048static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index f6edc2ff5494..77c0768d5bd8 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -2108,70 +2108,69 @@ static struct tegra_function tegra30_functions[] = {
2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2109#define PINGROUP_REG_A 0x3000 /* bank 1 */ 2109#define PINGROUP_REG_A 0x3000 /* bank 1 */
2110 2110
2111#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
2111#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 2112#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
2112 2113
2113#define PINGROUP_BIT_Y(b) (b) 2114#define PINGROUP_BIT_Y(b) (b)
2114#define PINGROUP_BIT_N(b) (-1) 2115#define PINGROUP_BIT_N(b) (-1)
2115 2116
2116#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \ 2117#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
2117 { \ 2118 { \
2118 .name = #pg_name, \ 2119 .name = #pg_name, \
2119 .pins = pg_name##_pins, \ 2120 .pins = pg_name##_pins, \
2120 .npins = ARRAY_SIZE(pg_name##_pins), \ 2121 .npins = ARRAY_SIZE(pg_name##_pins), \
2121 .funcs = { \ 2122 .funcs = { \
2122 TEGRA_MUX_##f0, \ 2123 TEGRA_MUX_##f0, \
2123 TEGRA_MUX_##f1, \ 2124 TEGRA_MUX_##f1, \
2124 TEGRA_MUX_##f2, \ 2125 TEGRA_MUX_##f2, \
2125 TEGRA_MUX_##f3, \ 2126 TEGRA_MUX_##f3, \
2126 }, \ 2127 }, \
2127 .mux_reg = PINGROUP_REG(r), \ 2128 .mux_reg = PINGROUP_REG(r), \
2128 .mux_bank = 1, \ 2129 .mux_bank = 1, \
2129 .mux_bit = 0, \ 2130 .mux_bit = 0, \
2130 .pupd_reg = PINGROUP_REG(r), \ 2131 .pupd_reg = PINGROUP_REG(r), \
2131 .pupd_bank = 1, \ 2132 .pupd_bank = 1, \
2132 .pupd_bit = 2, \ 2133 .pupd_bit = 2, \
2133 .tri_reg = PINGROUP_REG(r), \ 2134 .tri_reg = PINGROUP_REG(r), \
2134 .tri_bank = 1, \ 2135 .tri_bank = 1, \
2135 .tri_bit = 4, \ 2136 .tri_bit = 4, \
2136 .einput_bit = PINGROUP_BIT_Y(5), \ 2137 .einput_bit = 5, \
2137 .odrain_bit = PINGROUP_BIT_##od(6), \ 2138 .odrain_bit = PINGROUP_BIT_##od(6), \
2138 .lock_bit = PINGROUP_BIT_Y(7), \ 2139 .lock_bit = 7, \
2139 .ioreset_bit = PINGROUP_BIT_##ior(8), \ 2140 .ioreset_bit = PINGROUP_BIT_##ior(8), \
2140 .rcv_sel_bit = -1, \ 2141 .rcv_sel_bit = -1, \
2141 .drv_reg = -1, \ 2142 .drv_reg = -1, \
2142 } 2143 }
2143 2144
2144#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) 2145#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
2145 2146 drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
2146#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 2147 slwf_b, slwf_w) \
2147 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 2148 { \
2148 slwr_b, slwr_w, slwf_b, slwf_w) \ 2149 .name = "drive_" #pg_name, \
2149 { \ 2150 .pins = drive_##pg_name##_pins, \
2150 .name = "drive_" #pg_name, \ 2151 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2151 .pins = drive_##pg_name##_pins, \ 2152 .mux_reg = -1, \
2152 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ 2153 .pupd_reg = -1, \
2153 .mux_reg = -1, \ 2154 .tri_reg = -1, \
2154 .pupd_reg = -1, \ 2155 .einput_bit = -1, \
2155 .tri_reg = -1, \ 2156 .odrain_bit = -1, \
2156 .einput_bit = -1, \ 2157 .lock_bit = -1, \
2157 .odrain_bit = -1, \ 2158 .ioreset_bit = -1, \
2158 .lock_bit = -1, \ 2159 .rcv_sel_bit = -1, \
2159 .ioreset_bit = -1, \ 2160 .drv_reg = DRV_PINGROUP_REG(r), \
2160 .rcv_sel_bit = -1, \ 2161 .drv_bank = 0, \
2161 .drv_reg = DRV_PINGROUP_REG(r), \ 2162 .hsm_bit = hsm_b, \
2162 .drv_bank = 0, \ 2163 .schmitt_bit = schmitt_b, \
2163 .hsm_bit = hsm_b, \ 2164 .lpmd_bit = lpmd_b, \
2164 .schmitt_bit = schmitt_b, \ 2165 .drvdn_bit = drvdn_b, \
2165 .lpmd_bit = lpmd_b, \ 2166 .drvdn_width = drvdn_w, \
2166 .drvdn_bit = drvdn_b, \ 2167 .drvup_bit = drvup_b, \
2167 .drvdn_width = drvdn_w, \ 2168 .drvup_width = drvup_w, \
2168 .drvup_bit = drvup_b, \ 2169 .slwr_bit = slwr_b, \
2169 .drvup_width = drvup_w, \ 2170 .slwr_width = slwr_w, \
2170 .slwr_bit = slwr_b, \ 2171 .slwf_bit = slwf_b, \
2171 .slwr_width = slwr_w, \ 2172 .slwf_width = slwf_w, \
2172 .slwf_bit = slwf_b, \ 2173 .drvtype_bit = -1, \
2173 .slwf_width = slwf_w, \
2174 .drvtype_bit = -1, \
2175 } 2174 }
2176 2175
2177static const struct tegra_pingroup tegra30_groups[] = { 2176static const struct tegra_pingroup tegra30_groups[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 16:26:19 -0400