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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-04-17 05:06:46 -0400
committerDaniel Lezcano <daniel.lezcano@linaro.org>2014-04-22 07:56:50 -0400
commit8cffcb0ca33381e07cee4ebe1301d0794054fc97 (patch)
treef4eab12ecd620b78dfed2a1e2331c1e3e62b0bfd
parente50a00be5c420b4f28836dec281cdde4bed832a2 (diff)
ARM: sun6i: a31: Add support for the High Speed Timers
The Allwinner A31 has support for four high speed timers. Apart for the number of timers (4 vs 2), it's basically the same logic than the high speed timers found in the sun5i chips. Now that we have a driver to support it, we can enable them in the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index d45efa74827c..8cee8a15b90b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -428,6 +428,17 @@
428 status = "disabled"; 428 status = "disabled";
429 }; 429 };
430 430
431 timer@01c60000 {
432 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
433 reg = <0x01c60000 0x1000>;
434 interrupts = <0 51 4>,
435 <0 52 4>,
436 <0 53 4>,
437 <0 54 4>;
438 clocks = <&ahb1_gates 19>;
439 resets = <&ahb1_rst 19>;
440 };
441
431 spi0: spi@01c68000 { 442 spi0: spi@01c68000 {
432 compatible = "allwinner,sun6i-a31-spi"; 443 compatible = "allwinner,sun6i-a31-spi";
433 reg = <0x01c68000 0x1000>; 444 reg = <0x01c68000 0x1000>;