diff options
author | Anders Berg <anders.berg@lsi.com> | 2014-05-23 05:08:36 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2014-05-23 12:18:45 -0400 |
commit | 8cee8af2ac17302960bf2030820512f0f9848014 (patch) | |
tree | dce6ba62d99d88c5eef14b943119824c7d418ede | |
parent | 1d22924e1c4e299337e86e290c02c3e3eb43b608 (diff) |
ARM: dts: Device tree for AXM55xx.
Add device tree for the Amarillo validation board with an AXM5516 SoC.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r-- | arch/arm/boot/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/boot/dts/axm5516-amarillo.dts | 51 | ||||
-rw-r--r-- | arch/arm/boot/dts/axm5516-cpus.dtsi | 204 | ||||
-rw-r--r-- | arch/arm/boot/dts/axm55xx.dtsi | 199 |
4 files changed, 455 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..f73797f7ff48 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
@@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb | |||
50 | dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb | 50 | dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb |
51 | 51 | ||
52 | dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb | 52 | dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb |
53 | dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb | ||
53 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb | 54 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
54 | dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ | 55 | dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ |
55 | bcm21664-garnet.dtb | 56 | bcm21664-garnet.dtb |
diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/axm5516-amarillo.dts new file mode 100644 index 000000000000..a9d60471d9ff --- /dev/null +++ b/arch/arm/boot/dts/axm5516-amarillo.dts | |||
@@ -0,0 +1,51 @@ | |||
1 | /* | ||
2 | * arch/arm/boot/dts/axm5516-amarillo.dts | ||
3 | * | ||
4 | * Copyright (C) 2013 LSI | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | /dts-v1/; | ||
13 | |||
14 | /memreserve/ 0x00000000 0x00400000; | ||
15 | |||
16 | #include "axm55xx.dtsi" | ||
17 | #include "axm5516-cpus.dtsi" | ||
18 | |||
19 | / { | ||
20 | model = "Amarillo AXM5516"; | ||
21 | compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; | ||
22 | |||
23 | memory { | ||
24 | device_type = "memory"; | ||
25 | reg = <0 0x00000000 0x02 0x00000000>; | ||
26 | }; | ||
27 | }; | ||
28 | |||
29 | &serial0 { | ||
30 | status = "okay"; | ||
31 | }; | ||
32 | |||
33 | &serial1 { | ||
34 | status = "okay"; | ||
35 | }; | ||
36 | |||
37 | &serial2 { | ||
38 | status = "okay"; | ||
39 | }; | ||
40 | |||
41 | &serial3 { | ||
42 | status = "okay"; | ||
43 | }; | ||
44 | |||
45 | &gpio0 { | ||
46 | status = "okay"; | ||
47 | }; | ||
48 | |||
49 | &gpio1 { | ||
50 | status = "okay"; | ||
51 | }; | ||
diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi new file mode 100644 index 000000000000..b85f360cb125 --- /dev/null +++ b/arch/arm/boot/dts/axm5516-cpus.dtsi | |||
@@ -0,0 +1,204 @@ | |||
1 | /* | ||
2 | * arch/arm/boot/dts/axm5516-cpus.dtsi | ||
3 | * | ||
4 | * Copyright (C) 2013 LSI | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | / { | ||
13 | cpus { | ||
14 | #address-cells = <1>; | ||
15 | #size-cells = <0>; | ||
16 | |||
17 | cpu-map { | ||
18 | cluster0 { | ||
19 | core0 { | ||
20 | cpu = <&CPU0>; | ||
21 | }; | ||
22 | core1 { | ||
23 | cpu = <&CPU1>; | ||
24 | }; | ||
25 | core2 { | ||
26 | cpu = <&CPU2>; | ||
27 | }; | ||
28 | core3 { | ||
29 | cpu = <&CPU3>; | ||
30 | }; | ||
31 | }; | ||
32 | cluster1 { | ||
33 | core0 { | ||
34 | cpu = <&CPU4>; | ||
35 | }; | ||
36 | core1 { | ||
37 | cpu = <&CPU5>; | ||
38 | }; | ||
39 | core2 { | ||
40 | cpu = <&CPU6>; | ||
41 | }; | ||
42 | core3 { | ||
43 | cpu = <&CPU7>; | ||
44 | }; | ||
45 | }; | ||
46 | cluster2 { | ||
47 | core0 { | ||
48 | cpu = <&CPU8>; | ||
49 | }; | ||
50 | core1 { | ||
51 | cpu = <&CPU9>; | ||
52 | }; | ||
53 | core2 { | ||
54 | cpu = <&CPU10>; | ||
55 | }; | ||
56 | core3 { | ||
57 | cpu = <&CPU11>; | ||
58 | }; | ||
59 | }; | ||
60 | cluster3 { | ||
61 | core0 { | ||
62 | cpu = <&CPU12>; | ||
63 | }; | ||
64 | core1 { | ||
65 | cpu = <&CPU13>; | ||
66 | }; | ||
67 | core2 { | ||
68 | cpu = <&CPU14>; | ||
69 | }; | ||
70 | core3 { | ||
71 | cpu = <&CPU15>; | ||
72 | }; | ||
73 | }; | ||
74 | }; | ||
75 | |||
76 | CPU0: cpu@0 { | ||
77 | device_type = "cpu"; | ||
78 | compatible = "arm,cortex-a15"; | ||
79 | reg = <0x00>; | ||
80 | clock-frequency= <1400000000>; | ||
81 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
82 | }; | ||
83 | |||
84 | CPU1: cpu@1 { | ||
85 | device_type = "cpu"; | ||
86 | compatible = "arm,cortex-a15"; | ||
87 | reg = <0x01>; | ||
88 | clock-frequency= <1400000000>; | ||
89 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
90 | }; | ||
91 | |||
92 | CPU2: cpu@2 { | ||
93 | device_type = "cpu"; | ||
94 | compatible = "arm,cortex-a15"; | ||
95 | reg = <0x02>; | ||
96 | clock-frequency= <1400000000>; | ||
97 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
98 | }; | ||
99 | |||
100 | CPU3: cpu@3 { | ||
101 | device_type = "cpu"; | ||
102 | compatible = "arm,cortex-a15"; | ||
103 | reg = <0x03>; | ||
104 | clock-frequency= <1400000000>; | ||
105 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
106 | }; | ||
107 | |||
108 | CPU4: cpu@100 { | ||
109 | device_type = "cpu"; | ||
110 | compatible = "arm,cortex-a15"; | ||
111 | reg = <0x100>; | ||
112 | clock-frequency= <1400000000>; | ||
113 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
114 | }; | ||
115 | |||
116 | CPU5: cpu@101 { | ||
117 | device_type = "cpu"; | ||
118 | compatible = "arm,cortex-a15"; | ||
119 | reg = <0x101>; | ||
120 | clock-frequency= <1400000000>; | ||
121 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
122 | }; | ||
123 | |||
124 | CPU6: cpu@102 { | ||
125 | device_type = "cpu"; | ||
126 | compatible = "arm,cortex-a15"; | ||
127 | reg = <0x102>; | ||
128 | clock-frequency= <1400000000>; | ||
129 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
130 | }; | ||
131 | |||
132 | CPU7: cpu@103 { | ||
133 | device_type = "cpu"; | ||
134 | compatible = "arm,cortex-a15"; | ||
135 | reg = <0x103>; | ||
136 | clock-frequency= <1400000000>; | ||
137 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
138 | }; | ||
139 | |||
140 | CPU8: cpu@200 { | ||
141 | device_type = "cpu"; | ||
142 | compatible = "arm,cortex-a15"; | ||
143 | reg = <0x200>; | ||
144 | clock-frequency= <1400000000>; | ||
145 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
146 | }; | ||
147 | |||
148 | CPU9: cpu@201 { | ||
149 | device_type = "cpu"; | ||
150 | compatible = "arm,cortex-a15"; | ||
151 | reg = <0x201>; | ||
152 | clock-frequency= <1400000000>; | ||
153 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
154 | }; | ||
155 | |||
156 | CPU10: cpu@202 { | ||
157 | device_type = "cpu"; | ||
158 | compatible = "arm,cortex-a15"; | ||
159 | reg = <0x202>; | ||
160 | clock-frequency= <1400000000>; | ||
161 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
162 | }; | ||
163 | |||
164 | CPU11: cpu@203 { | ||
165 | device_type = "cpu"; | ||
166 | compatible = "arm,cortex-a15"; | ||
167 | reg = <0x203>; | ||
168 | clock-frequency= <1400000000>; | ||
169 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
170 | }; | ||
171 | |||
172 | CPU12: cpu@300 { | ||
173 | device_type = "cpu"; | ||
174 | compatible = "arm,cortex-a15"; | ||
175 | reg = <0x300>; | ||
176 | clock-frequency= <1400000000>; | ||
177 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
178 | }; | ||
179 | |||
180 | CPU13: cpu@301 { | ||
181 | device_type = "cpu"; | ||
182 | compatible = "arm,cortex-a15"; | ||
183 | reg = <0x301>; | ||
184 | clock-frequency= <1400000000>; | ||
185 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
186 | }; | ||
187 | |||
188 | CPU14: cpu@302 { | ||
189 | device_type = "cpu"; | ||
190 | compatible = "arm,cortex-a15"; | ||
191 | reg = <0x302>; | ||
192 | clock-frequency= <1400000000>; | ||
193 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
194 | }; | ||
195 | |||
196 | CPU15: cpu@303 { | ||
197 | device_type = "cpu"; | ||
198 | compatible = "arm,cortex-a15"; | ||
199 | reg = <0x303>; | ||
200 | clock-frequency= <1400000000>; | ||
201 | cpu-release-addr = <0>; // Fixed by the boot loader | ||
202 | }; | ||
203 | }; | ||
204 | }; | ||
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi new file mode 100644 index 000000000000..3fbd83c2a179 --- /dev/null +++ b/arch/arm/boot/dts/axm55xx.dtsi | |||
@@ -0,0 +1,199 @@ | |||
1 | /* | ||
2 | * arch/arm/boot/dts/axm55xx.dtsi | ||
3 | * | ||
4 | * Copyright (C) 2013 LSI | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
13 | #include <dt-bindings/clock/lsi,axm5516-clks.h> | ||
14 | |||
15 | #include "skeleton64.dtsi" | ||
16 | |||
17 | / { | ||
18 | interrupt-parent = <&gic>; | ||
19 | |||
20 | aliases { | ||
21 | serial0 = &serial0; | ||
22 | serial1 = &serial1; | ||
23 | serial2 = &serial2; | ||
24 | serial3 = &serial3; | ||
25 | timer = &timer0; | ||
26 | }; | ||
27 | |||
28 | clocks { | ||
29 | compatible = "simple-bus"; | ||
30 | #address-cells = <2>; | ||
31 | #size-cells = <2>; | ||
32 | ranges; | ||
33 | |||
34 | clk_ref0: clk_ref0 { | ||
35 | compatible = "fixed-clock"; | ||
36 | #clock-cells = <0>; | ||
37 | clock-frequency = <125000000>; | ||
38 | }; | ||
39 | |||
40 | clk_ref1: clk_ref1 { | ||
41 | compatible = "fixed-clock"; | ||
42 | #clock-cells = <0>; | ||
43 | clock-frequency = <125000000>; | ||
44 | }; | ||
45 | |||
46 | clk_ref2: clk_ref2 { | ||
47 | compatible = "fixed-clock"; | ||
48 | #clock-cells = <0>; | ||
49 | clock-frequency = <125000000>; | ||
50 | }; | ||
51 | |||
52 | clks: clock-controller@2010020000 { | ||
53 | compatible = "lsi,axm5516-clks"; | ||
54 | #clock-cells = <1>; | ||
55 | reg = <0x20 0x10020000 0 0x20000>; | ||
56 | }; | ||
57 | }; | ||
58 | |||
59 | gic: interrupt-controller@2001001000 { | ||
60 | compatible = "arm,cortex-a15-gic"; | ||
61 | #interrupt-cells = <3>; | ||
62 | #address-cells = <0>; | ||
63 | interrupt-controller; | ||
64 | reg = <0x20 0x01001000 0 0x1000>, | ||
65 | <0x20 0x01002000 0 0x1000>, | ||
66 | <0x20 0x01004000 0 0x2000>, | ||
67 | <0x20 0x01006000 0 0x2000>; | ||
68 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | | ||
69 | IRQ_TYPE_LEVEL_HIGH)>; | ||
70 | }; | ||
71 | |||
72 | timer { | ||
73 | compatible = "arm,armv7-timer"; | ||
74 | interrupts = | ||
75 | <GIC_PPI 13 | ||
76 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
77 | <GIC_PPI 14 | ||
78 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
79 | <GIC_PPI 11 | ||
80 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
81 | <GIC_PPI 10 | ||
82 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | ||
83 | }; | ||
84 | |||
85 | |||
86 | pmu { | ||
87 | compatible = "arm,cortex-a15-pmu"; | ||
88 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | ||
89 | }; | ||
90 | |||
91 | soc { | ||
92 | compatible = "simple-bus"; | ||
93 | device_type = "soc"; | ||
94 | #address-cells = <2>; | ||
95 | #size-cells = <2>; | ||
96 | interrupt-parent = <&gic>; | ||
97 | ranges; | ||
98 | |||
99 | syscon: syscon@2010030000 { | ||
100 | compatible = "lsi,axxia-syscon", "syscon"; | ||
101 | reg = <0x20 0x10030000 0 0x2000>; | ||
102 | }; | ||
103 | |||
104 | amba { | ||
105 | compatible = "arm,amba-bus"; | ||
106 | #address-cells = <2>; | ||
107 | #size-cells = <2>; | ||
108 | ranges; | ||
109 | |||
110 | serial0: uart@2010080000 { | ||
111 | compatible = "arm,pl011", "arm,primecell"; | ||
112 | reg = <0x20 0x10080000 0 0x1000>; | ||
113 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | ||
114 | clocks = <&clks AXXIA_CLK_PER>; | ||
115 | clock-names = "apb_pclk"; | ||
116 | status = "disabled"; | ||
117 | }; | ||
118 | |||
119 | serial1: uart@2010081000 { | ||
120 | compatible = "arm,pl011", "arm,primecell"; | ||
121 | reg = <0x20 0x10081000 0 0x1000>; | ||
122 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | ||
123 | clocks = <&clks AXXIA_CLK_PER>; | ||
124 | clock-names = "apb_pclk"; | ||
125 | status = "disabled"; | ||
126 | }; | ||
127 | |||
128 | serial2: uart@2010082000 { | ||
129 | compatible = "arm,pl011", "arm,primecell"; | ||
130 | reg = <0x20 0x10082000 0 0x1000>; | ||
131 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | ||
132 | clocks = <&clks AXXIA_CLK_PER>; | ||
133 | clock-names = "apb_pclk"; | ||
134 | status = "disabled"; | ||
135 | }; | ||
136 | |||
137 | serial3: uart@2010083000 { | ||
138 | compatible = "arm,pl011", "arm,primecell"; | ||
139 | reg = <0x20 0x10083000 0 0x1000>; | ||
140 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | ||
141 | clocks = <&clks AXXIA_CLK_PER>; | ||
142 | clock-names = "apb_pclk"; | ||
143 | status = "disabled"; | ||
144 | }; | ||
145 | |||
146 | timer0: timer@2010091000 { | ||
147 | compatible = "arm,sp804", "arm,primecell"; | ||
148 | reg = <0x20 0x10091000 0 0x1000>; | ||
149 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | ||
150 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | ||
151 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | ||
152 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | ||
153 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | ||
154 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | ||
155 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | ||
156 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | ||
157 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | ||
158 | clocks = <&clks AXXIA_CLK_PER>; | ||
159 | clock-names = "apb_pclk"; | ||
160 | status = "okay"; | ||
161 | }; | ||
162 | |||
163 | gpio0: gpio@2010092000 { | ||
164 | #gpio-cells = <2>; | ||
165 | compatible = "arm,pl061", "arm,primecell"; | ||
166 | gpio-controller; | ||
167 | reg = <0x20 0x10092000 0x00 0x1000>; | ||
168 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | ||
169 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | ||
170 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | ||
171 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | ||
172 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | ||
173 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | ||
174 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | ||
175 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | ||
176 | clocks = <&clks AXXIA_CLK_PER>; | ||
177 | clock-names = "apb_pclk"; | ||
178 | status = "disabled"; | ||
179 | }; | ||
180 | |||
181 | gpio1: gpio@2010093000 { | ||
182 | #gpio-cells = <2>; | ||
183 | compatible = "arm,pl061", "arm,primecell"; | ||
184 | gpio-controller; | ||
185 | reg = <0x20 0x10093000 0x00 0x1000>; | ||
186 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | ||
187 | clocks = <&clks AXXIA_CLK_PER>; | ||
188 | clock-names = "apb_pclk"; | ||
189 | status = "disabled"; | ||
190 | }; | ||
191 | }; | ||
192 | }; | ||
193 | }; | ||
194 | |||
195 | /* | ||
196 | Local Variables: | ||
197 | mode: C | ||
198 | End: | ||
199 | */ | ||