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authorSheng Yang <sheng.yang@intel.com>2008-04-24 22:17:08 -0400
committerAvi Kivity <avi@qumranet.com>2008-05-04 05:26:38 -0400
commit8c6d6adc6b87daa364ee9deb2e966021d37a7622 (patch)
tree125cac3e4fa7a3495880e7b1c942e85eb6ea6bc6
parentd56f546db97795dca5aa575b00b0e9886895ac87 (diff)
KVM: MMU: Move some definitions to a header file
Move some definitions to mmu.h in order to allow building common table entries between EPT and non-EPT. Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
-rw-r--r--arch/x86/kvm/mmu.c34
-rw-r--r--arch/x86/kvm/mmu.h33
2 files changed, 33 insertions, 34 deletions
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 2ad6f5481671..bcfaf7e4a2dc 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -79,36 +79,6 @@ static int dbg = 1;
79 } 79 }
80#endif 80#endif
81 81
82#define PT64_PT_BITS 9
83#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
84#define PT32_PT_BITS 10
85#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
86
87#define PT_WRITABLE_SHIFT 1
88
89#define PT_PRESENT_MASK (1ULL << 0)
90#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
91#define PT_USER_MASK (1ULL << 2)
92#define PT_PWT_MASK (1ULL << 3)
93#define PT_PCD_MASK (1ULL << 4)
94#define PT_ACCESSED_MASK (1ULL << 5)
95#define PT_DIRTY_MASK (1ULL << 6)
96#define PT_PAGE_SIZE_MASK (1ULL << 7)
97#define PT_PAT_MASK (1ULL << 7)
98#define PT_GLOBAL_MASK (1ULL << 8)
99#define PT64_NX_SHIFT 63
100#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
101
102#define PT_PAT_SHIFT 7
103#define PT_DIR_PAT_SHIFT 12
104#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
105
106#define PT32_DIR_PSE36_SIZE 4
107#define PT32_DIR_PSE36_SHIFT 13
108#define PT32_DIR_PSE36_MASK \
109 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
110
111
112#define PT_FIRST_AVAIL_BITS_SHIFT 9 82#define PT_FIRST_AVAIL_BITS_SHIFT 9
113#define PT64_SECOND_AVAIL_BITS_SHIFT 52 83#define PT64_SECOND_AVAIL_BITS_SHIFT 52
114 84
@@ -154,10 +124,6 @@ static int dbg = 1;
154#define PFERR_USER_MASK (1U << 2) 124#define PFERR_USER_MASK (1U << 2)
155#define PFERR_FETCH_MASK (1U << 4) 125#define PFERR_FETCH_MASK (1U << 4)
156 126
157#define PT64_ROOT_LEVEL 4
158#define PT32_ROOT_LEVEL 2
159#define PT32E_ROOT_LEVEL 3
160
161#define PT_DIRECTORY_LEVEL 2 127#define PT_DIRECTORY_LEVEL 2
162#define PT_PAGE_TABLE_LEVEL 1 128#define PT_PAGE_TABLE_LEVEL 1
163 129
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index e64e9f56a65e..a4fcb78ebf42 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -9,6 +9,39 @@
9#define TDP_ROOT_LEVEL PT32E_ROOT_LEVEL 9#define TDP_ROOT_LEVEL PT32E_ROOT_LEVEL
10#endif 10#endif
11 11
12#define PT64_PT_BITS 9
13#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
14#define PT32_PT_BITS 10
15#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
16
17#define PT_WRITABLE_SHIFT 1
18
19#define PT_PRESENT_MASK (1ULL << 0)
20#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
21#define PT_USER_MASK (1ULL << 2)
22#define PT_PWT_MASK (1ULL << 3)
23#define PT_PCD_MASK (1ULL << 4)
24#define PT_ACCESSED_MASK (1ULL << 5)
25#define PT_DIRTY_MASK (1ULL << 6)
26#define PT_PAGE_SIZE_MASK (1ULL << 7)
27#define PT_PAT_MASK (1ULL << 7)
28#define PT_GLOBAL_MASK (1ULL << 8)
29#define PT64_NX_SHIFT 63
30#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
31
32#define PT_PAT_SHIFT 7
33#define PT_DIR_PAT_SHIFT 12
34#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
35
36#define PT32_DIR_PSE36_SIZE 4
37#define PT32_DIR_PSE36_SHIFT 13
38#define PT32_DIR_PSE36_MASK \
39 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
40
41#define PT64_ROOT_LEVEL 4
42#define PT32_ROOT_LEVEL 2
43#define PT32E_ROOT_LEVEL 3
44
12static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) 45static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
13{ 46{
14 if (unlikely(vcpu->kvm->arch.n_free_mmu_pages < KVM_MIN_FREE_MMU_PAGES)) 47 if (unlikely(vcpu->kvm->arch.n_free_mmu_pages < KVM_MIN_FREE_MMU_PAGES))