bcma: implement host code support for PCIe Gen 2 devices

This is stil incomplete, so we don't add PCI IDs of new devices yet.
Purpose of this patch is to allow testing & adjusting rest of the code.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

3 files changed, 7 insertions, 2 deletions

diff --git a/drivers/bcma/host_pci.c b/drivers/bcma/host_pci.c
index cd9161a8b3a1..53c6a8a58859 100644
--- a/drivers/bcma/host_pci.c
+++ b/drivers/bcma/host_pci.c
@@ -13,10 +13,12 @@
 
 static void bcma_host_pci_switch_core(struct bcma_device *core)
 {
+        int win2 = core->bus->host_is_pcie2 ?
+                BCMA_PCIE2_BAR0_WIN2 : BCMA_PCI_BAR0_WIN2;
+
         pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
                                core->addr);
-        pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
-                               core->wrap);
+        pci_write_config_dword(core->bus->host_pci, win2, core->wrap);
         core->bus->mapped_core = core;
         bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
 }
diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
index eb1c6a47b67f..994739da827f 100644
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
@@ -318,6 +318,7 @@ struct bcma_bus {
         const struct bcma_host_ops *ops;
 
         enum bcma_hosttype hosttype;
+        bool host_is_pcie2; /* Used for BCMA_HOSTTYPE_PCI only */
         union {
                 /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
                 struct pci_dev *host_pci;
diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h
index e64ae7bf80a1..ebd5c1fcdea4 100644
--- a/include/linux/bcma/bcma_regs.h
+++ b/include/linux/bcma/bcma_regs.h
@@ -64,6 +64,8 @@
 #define  BCMA_PCI_GPIO_XTAL             0x40    /* PCI config space GPIO 14 for Xtal powerup */
 #define  BCMA_PCI_GPIO_PLL              0x80    /* PCI config space GPIO 15 for PLL powerdown */
 
+#define BCMA_PCIE2_BAR0_WIN2            0x70
+
 /* SiliconBackplane Address Map.
  * All regions may not exist on all chips.
  */