ARM: DT: APQ8064: Add pinctrl support

This patch adds device tree nodes to support pinctrl for apq8064 SOC

CC: Rob Herring <robh+dt@kernel.org>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: devicetree@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org

Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

1 files changed, 12 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92bf793622c3..23745f264212 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -3,6 +3,7 @@
 #include "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
         model = "Qualcomm APQ8064";
@@ -70,6 +71,17 @@
                 ranges;
                 compatible = "simple-bus";
 
+                tlmm_pinmux: pinctrl@800000 {
+                        compatible = "qcom,apq8064-pinctrl";
+                        reg = <0x800000 0x4000>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
                 intc: interrupt-controller@2000000 {
                         compatible = "qcom,msm-qgic2";
                         interrupt-controller;