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authorOlof Johansson <olof@lixom.net>2013-04-18 01:26:15 -0400
committerOlof Johansson <olof@lixom.net>2013-04-18 01:26:25 -0400
commit8b85143e5dc428e8023bd741dfa9ec2e64ff4525 (patch)
treec7bdc555c5ac39c8ce6850e575e3906666cc05d2
parent567b1b0839150e8d701553cbb586365b1f2ed36c (diff)
parentda497f6fbaa190d34907ecc9dd85cfc62ba9f5a2 (diff)
Merge tag 'soc_for_v3.10' of git://git.infradead.org/users/jcooper/linux into next/soc2
From Jason Cooper: mvebu soc changes for v3.10 - use the mvebu-mbus driver - prep for LPAE support Depends: - mvebu/cleanup (tags/cleanup_for_v3.10) - mvebu/drivers (tags/drivers_for_v3.10) * tag 'soc_for_v3.10' of git://git.infradead.org/users/jcooper/linux: ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver bus: mvebu: fix mistake in PCIe window target attribute for Kirkwood bus: mvebu-mbus: Restore checking for coherency fabric hardware ARM: Orion: add dbg_show function to gpio-orion driver bus: introduce an Marvell EBU MBus driver arm: mach-orion5x: use mv_mbus_dram_info() in PCI code arm: plat-orion: use mv_mbus_dram_info() in PCIe code arm: plat-orion: only build addr-map.c when needed Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi5
-rw-r--r--arch/arm/include/debug/mvebu.S2
-rw-r--r--arch/arm/mach-dove/Makefile2
-rw-r--r--arch/arm/mach-dove/addr-map.c125
-rw-r--r--arch/arm/mach-dove/board-dt.c2
-rw-r--r--arch/arm/mach-dove/common.c39
-rw-r--r--arch/arm/mach-dove/common.h2
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h5
-rw-r--r--arch/arm/mach-kirkwood/Makefile2
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c91
-rw-r--r--arch/arm/mach-kirkwood/board-dt.c2
-rw-r--r--arch/arm/mach-kirkwood/common.c38
-rw-r--r--arch/arm/mach-kirkwood/common.h2
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h7
-rw-r--r--arch/arm/mach-kirkwood/pcie.c1
-rw-r--r--arch/arm/mach-mv78xx0/Makefile2
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c93
-rw-r--r--arch/arm/mach-mv78xx0/common.c10
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/mv78xx0.h9
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c21
-rw-r--r--arch/arm/mach-mvebu/Kconfig2
-rw-r--r--arch/arm/mach-mvebu/Makefile2
-rw-r--r--arch/arm/mach-mvebu/addr-map.c137
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c18
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.h8
-rw-r--r--arch/arm/mach-mvebu/platsmp.c2
-rw-r--r--arch/arm/mach-orion5x/Makefile2
-rw-r--r--arch/arm/mach-orion5x/addr-map.c155
-rw-r--r--arch/arm/mach-orion5x/board-dt.c2
-rw-r--r--arch/arm/mach-orion5x/common.c49
-rw-r--r--arch/arm/mach-orion5x/common.h13
-rw-r--r--arch/arm/mach-orion5x/d2net-setup.c4
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c13
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c3
-rw-r--r--arch/arm/mach-orion5x/edmini_v2-setup.c4
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h6
-rw-r--r--arch/arm/mach-orion5x/kurobox_pro-setup.c8
-rw-r--r--arch/arm/mach-orion5x/ls-chl-setup.c4
-rw-r--r--arch/arm/mach-orion5x/ls_hgl-setup.c4
-rw-r--r--arch/arm/mach-orion5x/lsmini-setup.c4
-rw-r--r--arch/arm/mach-orion5x/mss2-setup.c3
-rw-r--r--arch/arm/mach-orion5x/mv2120-setup.c3
-rw-r--r--arch/arm/mach-orion5x/net2big-setup.c4
-rw-r--r--arch/arm/mach-orion5x/pci.c14
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c4
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-ge-setup.c4
-rw-r--r--arch/arm/mach-orion5x/rd88f5182-setup.c7
-rw-r--r--arch/arm/mach-orion5x/terastation_pro2-setup.c4
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c4
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c4
-rw-r--r--arch/arm/mach-orion5x/wnr854t-setup.c4
-rw-r--r--arch/arm/mach-orion5x/wrt350n-v2-setup.c4
-rw-r--r--arch/arm/plat-orion/Makefile2
-rw-r--r--arch/arm/plat-orion/addr-map.c178
-rw-r--r--arch/arm/plat-orion/gpio.c59
-rw-r--r--arch/arm/plat-orion/pcie.c10
-rw-r--r--drivers/bus/Kconfig7
-rw-r--r--drivers/bus/Makefile1
-rw-r--r--drivers/bus/mvebu-mbus.c870
-rw-r--r--include/linux/mbus.h27
61 files changed, 1234 insertions, 883 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8d39c8ba9691..fe31c8c6b3e2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -562,6 +562,7 @@ config ARCH_DOVE
562 select PINCTRL_DOVE 562 select PINCTRL_DOVE
563 select PLAT_ORION_LEGACY 563 select PLAT_ORION_LEGACY
564 select USB_ARCH_HAS_EHCI 564 select USB_ARCH_HAS_EHCI
565 select MVEBU_MBUS
565 help 566 help
566 Support for the Marvell Dove SoC 88AP510 567 Support for the Marvell Dove SoC 88AP510
567 568
@@ -575,6 +576,7 @@ config ARCH_KIRKWOOD
575 select PINCTRL 576 select PINCTRL
576 select PINCTRL_KIRKWOOD 577 select PINCTRL_KIRKWOOD
577 select PLAT_ORION_LEGACY 578 select PLAT_ORION_LEGACY
579 select MVEBU_MBUS
578 help 580 help
579 Support for the following Marvell Kirkwood series SoCs: 581 Support for the following Marvell Kirkwood series SoCs:
580 88F6180, 88F6192 and 88F6281. 582 88F6180, 88F6192 and 88F6281.
@@ -586,6 +588,7 @@ config ARCH_MV78XX0
586 select GENERIC_CLOCKEVENTS 588 select GENERIC_CLOCKEVENTS
587 select PCI 589 select PCI
588 select PLAT_ORION_LEGACY 590 select PLAT_ORION_LEGACY
591 select MVEBU_MBUS
589 help 592 help
590 Support for the following Marvell MV78xx0 series SoCs: 593 Support for the following Marvell MV78xx0 series SoCs:
591 MV781x0, MV782x0. 594 MV781x0, MV782x0.
@@ -598,6 +601,7 @@ config ARCH_ORION5X
598 select GENERIC_CLOCKEVENTS 601 select GENERIC_CLOCKEVENTS
599 select PCI 602 select PCI
600 select PLAT_ORION_LEGACY 603 select PLAT_ORION_LEGACY
604 select MVEBU_MBUS
601 help 605 help
602 Support for the following Marvell Orion 5x series SoCs: 606 Support for the following Marvell Orion 5x series SoCs:
603 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 607 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 5b708208b607..7704829a12c0 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -73,11 +73,6 @@
73 clocks = <&coreclk 2>; 73 clocks = <&coreclk 2>;
74 }; 74 };
75 75
76 addr-decoding@d0020000 {
77 compatible = "marvell,armada-addr-decoding-controller";
78 reg = <0xd0020000 0x258>;
79 };
80
81 sata@d00a0000 { 76 sata@d00a0000 {
82 compatible = "marvell,orion-sata"; 77 compatible = "marvell,orion-sata";
83 reg = <0xd00a0000 0x2400>; 78 reg = <0xd00a0000 0x2400>;
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index 865c6d02b332..df191afa3be1 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -12,7 +12,7 @@
12*/ 12*/
13 13
14#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 14#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
15#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 15#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000
16 16
17 .macro addruart, rp, rv, tmp 17 .macro addruart, rp, rv, tmp
18 ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE 18 ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 3f0a858fb597..4d9d2ffc4535 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
1obj-y += common.o addr-map.o irq.o 1obj-y += common.o irq.o
2obj-$(CONFIG_DOVE_LEGACY) += mpp.o 2obj-$(CONFIG_DOVE_LEGACY) += mpp.o
3obj-$(CONFIG_PCI) += pcie.o 3obj-$(CONFIG_PCI) += pcie.o
4obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o 4obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
deleted file mode 100644
index 2a06c0163418..000000000000
--- a/arch/arm/mach-dove/addr-map.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * arch/arm/mach-dove/addr-map.c
3 *
4 * Address map functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <asm/mach/arch.h>
16#include <asm/setup.h>
17#include <mach/dove.h>
18#include <plat/addr-map.h>
19#include "common.h"
20
21/*
22 * Generic Address Decode Windows bit settings
23 */
24#define TARGET_DDR 0x0
25#define TARGET_BOOTROM 0x1
26#define TARGET_CESA 0x3
27#define TARGET_PCIE0 0x4
28#define TARGET_PCIE1 0x8
29#define TARGET_SCRATCHPAD 0xd
30
31#define ATTR_CESA 0x01
32#define ATTR_BOOTROM 0xfd
33#define ATTR_DEV_SPI0_ROM 0xfe
34#define ATTR_DEV_SPI1_ROM 0xfb
35#define ATTR_PCIE_IO 0xe0
36#define ATTR_PCIE_MEM 0xe8
37#define ATTR_SCRATCHPAD 0x0
38
39static inline void __iomem *ddr_map_sc(int i)
40{
41 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
42}
43
44/*
45 * Description of the windows needed by the platform code
46 */
47static struct __initdata orion_addr_map_cfg addr_map_cfg = {
48 .num_wins = 8,
49 .remappable_wins = 4,
50 .bridge_virt_base = BRIDGE_VIRT_BASE,
51};
52
53static const struct __initdata orion_addr_map_info addr_map_info[] = {
54 /*
55 * Windows for PCIe IO+MEM space.
56 */
57 { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
58 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
59 },
60 { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
61 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
62 },
63 { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
64 TARGET_PCIE0, ATTR_PCIE_MEM, -1
65 },
66 { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
67 TARGET_PCIE1, ATTR_PCIE_MEM, -1
68 },
69 /*
70 * Window for CESA engine.
71 */
72 { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
73 TARGET_CESA, ATTR_CESA, -1
74 },
75 /*
76 * Window to the BootROM for Standby and Sleep Resume
77 */
78 { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
79 TARGET_BOOTROM, ATTR_BOOTROM, -1
80 },
81 /*
82 * Window to the PMU Scratch Pad space
83 */
84 { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
85 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
86 },
87 /* End marker */
88 { -1, 0, 0, 0, 0, 0 }
89};
90
91void __init dove_setup_cpu_mbus(void)
92{
93 int i;
94 int cs;
95
96 /*
97 * Disable, clear and configure windows.
98 */
99 orion_config_wins(&addr_map_cfg, addr_map_info);
100
101 /*
102 * Setup MBUS dram target info.
103 */
104 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
105
106 for (i = 0, cs = 0; i < 2; i++) {
107 u32 map = readl(ddr_map_sc(i));
108
109 /*
110 * Chip select enabled?
111 */
112 if (map & 1) {
113 struct mbus_dram_window *w;
114
115 w = &orion_mbus_dram_info.cs[cs++];
116 w->cs_index = i;
117 w->mbus_attr = 0; /* CS address decoding done inside */
118 /* the DDR controller, no need to */
119 /* provide attributes */
120 w->base = map & 0xff800000;
121 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
122 }
123 }
124 orion_mbus_dram_info.num_cs = cs;
125}
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index fbde1dd67113..0b142803b2e1 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -64,7 +64,7 @@ static void __init dove_dt_init(void)
64#ifdef CONFIG_CACHE_TAUROS2 64#ifdef CONFIG_CACHE_TAUROS2
65 tauros2_init(0); 65 tauros2_init(0);
66#endif 66#endif
67 dove_setup_cpu_mbus(); 67 dove_setup_cpu_wins();
68 68
69 /* Setup root of clk tree */ 69 /* Setup root of clk tree */
70 dove_of_clk_init(); 70 dove_of_clk_init();
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index c6b3b2bb50e7..e2b5da031f96 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -224,6 +224,9 @@ void __init dove_i2c_init(void)
224void __init dove_init_early(void) 224void __init dove_init_early(void)
225{ 225{
226 orion_time_set_base(TIMER_VIRT_BASE); 226 orion_time_set_base(TIMER_VIRT_BASE);
227 mvebu_mbus_init("marvell,dove-mbus",
228 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
229 DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
227} 230}
228 231
229static int __init dove_find_tclk(void) 232static int __init dove_find_tclk(void)
@@ -326,6 +329,40 @@ void __init dove_sdio1_init(void)
326 platform_device_register(&dove_sdio1); 329 platform_device_register(&dove_sdio1);
327} 330}
328 331
332void __init dove_setup_cpu_wins(void)
333{
334 /*
335 * The PCIe windows will no longer be statically allocated
336 * here once Dove is migrated to the pci-mvebu driver.
337 */
338 mvebu_mbus_add_window_remap_flags("pcie0.0",
339 DOVE_PCIE0_IO_PHYS_BASE,
340 DOVE_PCIE0_IO_SIZE,
341 DOVE_PCIE0_IO_BUS_BASE,
342 MVEBU_MBUS_PCI_IO);
343 mvebu_mbus_add_window_remap_flags("pcie1.0",
344 DOVE_PCIE1_IO_PHYS_BASE,
345 DOVE_PCIE1_IO_SIZE,
346 DOVE_PCIE1_IO_BUS_BASE,
347 MVEBU_MBUS_PCI_IO);
348 mvebu_mbus_add_window_remap_flags("pcie0.0",
349 DOVE_PCIE0_MEM_PHYS_BASE,
350 DOVE_PCIE0_MEM_SIZE,
351 MVEBU_MBUS_NO_REMAP,
352 MVEBU_MBUS_PCI_MEM);
353 mvebu_mbus_add_window_remap_flags("pcie1.0",
354 DOVE_PCIE1_MEM_PHYS_BASE,
355 DOVE_PCIE1_MEM_SIZE,
356 MVEBU_MBUS_NO_REMAP,
357 MVEBU_MBUS_PCI_MEM);
358 mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
359 DOVE_CESA_SIZE);
360 mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
361 DOVE_BOOTROM_SIZE);
362 mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
363 DOVE_SCRATCHPAD_SIZE);
364}
365
329void __init dove_init(void) 366void __init dove_init(void)
330{ 367{
331 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 368 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
@@ -334,7 +371,7 @@ void __init dove_init(void)
334#ifdef CONFIG_CACHE_TAUROS2 371#ifdef CONFIG_CACHE_TAUROS2
335 tauros2_init(0); 372 tauros2_init(0);
336#endif 373#endif
337 dove_setup_cpu_mbus(); 374 dove_setup_cpu_wins();
338 375
339 /* Setup root of clk tree */ 376 /* Setup root of clk tree */
340 dove_clk_init(); 377 dove_clk_init();
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index ee59fba4c6d1..e86347928b67 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -23,7 +23,7 @@ void dove_map_io(void);
23void dove_init(void); 23void dove_init(void);
24void dove_init_early(void); 24void dove_init_early(void);
25void dove_init_irq(void); 25void dove_init_irq(void);
26void dove_setup_cpu_mbus(void); 26void dove_setup_cpu_wins(void);
27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); 27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
28void dove_sata_init(struct mv_sata_platform_data *sata_data); 28void dove_sata_init(struct mv_sata_platform_data *sata_data);
29#ifdef CONFIG_PCI 29#ifdef CONFIG_PCI
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 661725e3115a..0c4b35f4ee5b 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -77,6 +77,8 @@
77/* North-South Bridge */ 77/* North-South Bridge */
78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) 78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) 79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
80#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
81#define BRIDGE_WINS_SZ (0x80)
80 82
81/* Cryptographic Engine */ 83/* Cryptographic Engine */
82#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) 84#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
@@ -168,6 +170,9 @@
168#define DOVE_SSP_CLOCK_ENABLE (1 << 1) 170#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
169#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) 171#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
170/* Memory Controller */ 172/* Memory Controller */
173#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000)
174#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100)
175#define DOVE_MC_WINS_SZ (0x8)
171#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) 176#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
172 177
173/* LCD Controller */ 178/* LCD Controller */
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 4cc4bee4d0cf..d805f8078fa3 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,4 +1,4 @@
1obj-y += common.o addr-map.o irq.o pcie.o mpp.o 1obj-y += common.o irq.o pcie.o mpp.o
2 2
3obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o 3obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o
4obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o 4obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
deleted file mode 100644
index 8f0d162a1e1d..000000000000
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/addr-map.c
3 *
4 * Address map functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <mach/hardware.h>
16#include <plat/addr-map.h>
17#include "common.h"
18
19/*
20 * Generic Address Decode Windows bit settings
21 */
22#define TARGET_DEV_BUS 1
23#define TARGET_SRAM 3
24#define TARGET_PCIE 4
25#define ATTR_DEV_SPI_ROM 0x1e
26#define ATTR_DEV_BOOT 0x1d
27#define ATTR_DEV_NAND 0x2f
28#define ATTR_DEV_CS3 0x37
29#define ATTR_DEV_CS2 0x3b
30#define ATTR_DEV_CS1 0x3d
31#define ATTR_DEV_CS0 0x3e
32#define ATTR_PCIE_IO 0xe0
33#define ATTR_PCIE_MEM 0xe8
34#define ATTR_PCIE1_IO 0xd0
35#define ATTR_PCIE1_MEM 0xd8
36#define ATTR_SRAM 0x01
37
38/*
39 * Description of the windows needed by the platform code
40 */
41static struct __initdata orion_addr_map_cfg addr_map_cfg = {
42 .num_wins = 8,
43 .remappable_wins = 4,
44 .bridge_virt_base = BRIDGE_VIRT_BASE,
45};
46
47static const struct __initdata orion_addr_map_info addr_map_info[] = {
48 /*
49 * Windows for PCIe IO+MEM space.
50 */
51 { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
52 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
53 },
54 { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
55 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
56 },
57 { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
58 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
59 },
60 { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
61 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
62 },
63 /*
64 * Window for NAND controller.
65 */
66 { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
67 TARGET_DEV_BUS, ATTR_DEV_NAND, -1
68 },
69 /*
70 * Window for SRAM.
71 */
72 { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
73 TARGET_SRAM, ATTR_SRAM, -1
74 },
75 /* End marker */
76 { -1, 0, 0, 0, 0, 0 }
77};
78
79void __init kirkwood_setup_cpu_mbus(void)
80{
81 /*
82 * Disable, clear and configure windows.
83 */
84 orion_config_wins(&addr_map_cfg, addr_map_info);
85
86 /*
87 * Setup MBUS dram target info.
88 */
89 orion_setup_cpu_mbus_target(&addr_map_cfg,
90 (void __iomem *) DDR_WINDOW_CPU_BASE);
91}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index d367aa6b47bb..f5437c27dc2a 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -93,7 +93,7 @@ static void __init kirkwood_dt_init(void)
93 */ 93 */
94 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); 94 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
95 95
96 kirkwood_setup_cpu_mbus(); 96 kirkwood_setup_wins();
97 97
98 kirkwood_l2_init(); 98 kirkwood_l2_init();
99 99
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 49792a0cd2d3..c2cae69e6d2b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -33,7 +33,6 @@
33#include <linux/platform_data/usb-ehci-orion.h> 33#include <linux/platform_data/usb-ehci-orion.h>
34#include <plat/common.h> 34#include <plat/common.h>
35#include <plat/time.h> 35#include <plat/time.h>
36#include <plat/addr-map.h>
37#include <linux/platform_data/dma-mv_xor.h> 36#include <linux/platform_data/dma-mv_xor.h>
38#include "common.h" 37#include "common.h"
39 38
@@ -535,6 +534,9 @@ void __init kirkwood_init_early(void)
535 * the allocations won't fail. 534 * the allocations won't fail.
536 */ 535 */
537 init_dma_coherent_pool_size(SZ_1M); 536 init_dma_coherent_pool_size(SZ_1M);
537 mvebu_mbus_init("marvell,kirkwood-mbus",
538 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
539 DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
538} 540}
539 541
540int kirkwood_tclk; 542int kirkwood_tclk;
@@ -650,6 +652,38 @@ char * __init kirkwood_id(void)
650 } 652 }
651} 653}
652 654
655void __init kirkwood_setup_wins(void)
656{
657 /*
658 * The PCIe windows will no longer be statically allocated
659 * here once Kirkwood is migrated to the pci-mvebu driver.
660 */
661 mvebu_mbus_add_window_remap_flags("pcie0.0",
662 KIRKWOOD_PCIE_IO_PHYS_BASE,
663 KIRKWOOD_PCIE_IO_SIZE,
664 KIRKWOOD_PCIE_IO_BUS_BASE,
665 MVEBU_MBUS_PCI_IO);
666 mvebu_mbus_add_window_remap_flags("pcie0.0",
667 KIRKWOOD_PCIE_MEM_PHYS_BASE,
668 KIRKWOOD_PCIE_MEM_SIZE,
669 MVEBU_MBUS_NO_REMAP,
670 MVEBU_MBUS_PCI_MEM);
671 mvebu_mbus_add_window_remap_flags("pcie1.0",
672 KIRKWOOD_PCIE1_IO_PHYS_BASE,
673 KIRKWOOD_PCIE1_IO_SIZE,
674 KIRKWOOD_PCIE1_IO_BUS_BASE,
675 MVEBU_MBUS_PCI_IO);
676 mvebu_mbus_add_window_remap_flags("pcie1.0",
677 KIRKWOOD_PCIE1_MEM_PHYS_BASE,
678 KIRKWOOD_PCIE1_MEM_SIZE,
679 MVEBU_MBUS_NO_REMAP,
680 MVEBU_MBUS_PCI_MEM);
681 mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
682 KIRKWOOD_NAND_MEM_SIZE);
683 mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
684 KIRKWOOD_SRAM_SIZE);
685}
686
653void __init kirkwood_l2_init(void) 687void __init kirkwood_l2_init(void)
654{ 688{
655#ifdef CONFIG_CACHE_FEROCEON_L2 689#ifdef CONFIG_CACHE_FEROCEON_L2
@@ -675,7 +709,7 @@ void __init kirkwood_init(void)
675 */ 709 */
676 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); 710 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
677 711
678 kirkwood_setup_cpu_mbus(); 712 kirkwood_setup_wins();
679 713
680 kirkwood_l2_init(); 714 kirkwood_l2_init();
681 715
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5ed70565c843..e24f74305b34 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -30,7 +30,7 @@ void kirkwood_init(void);
30void kirkwood_init_early(void); 30void kirkwood_init_early(void);
31void kirkwood_init_irq(void); 31void kirkwood_init_irq(void);
32 32
33void kirkwood_setup_cpu_mbus(void); 33void kirkwood_setup_wins(void);
34 34
35void kirkwood_enable_pcie(void); 35void kirkwood_enable_pcie(void);
36void kirkwood_pcie_id(u32 *dev, u32 *rev); 36void kirkwood_pcie_id(u32 *dev, u32 *rev);
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a05563a31c95..92976cef3910 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -60,8 +60,9 @@
60 * Register Map 60 * Register Map
61 */ 61 */
62#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) 62#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
63#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) 63#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
64#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) 64#define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500)
65#define DDR_WINDOW_CPU_SZ (0x20)
65#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) 66#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
66 67
67#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) 68#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
@@ -80,6 +81,8 @@
80 81
81#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) 82#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
82#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) 83#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
84#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
85#define BRIDGE_WINS_SZ (0x80)
83 86
84#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) 87#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
85 88
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index d96ad4c09972..7f43e6c2f8c0 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -17,7 +17,6 @@
17#include <asm/mach/pci.h> 17#include <asm/mach/pci.h>
18#include <plat/pcie.h> 18#include <plat/pcie.h>
19#include <mach/bridge-regs.h> 19#include <mach/bridge-regs.h>
20#include <plat/addr-map.h>
21#include "common.h" 20#include "common.h"
22 21
23static void kirkwood_enable_pcie_clk(const char *port) 22static void kirkwood_enable_pcie_clk(const char *port)
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
index 67a13f9bfe64..7cd04634d302 100644
--- a/arch/arm/mach-mv78xx0/Makefile
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -1,4 +1,4 @@
1obj-y += common.o addr-map.o mpp.o irq.o pcie.o 1obj-y += common.o mpp.o irq.o pcie.o
2obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o 2obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o
3obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o 3obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o
4obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o 4obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
deleted file mode 100644
index 26e9876b50e9..000000000000
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * arch/arm/mach-mv78xx0/addr-map.c
3 *
4 * Address map functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <plat/addr-map.h>
16#include <mach/mv78xx0.h>
17#include "common.h"
18
19/*
20 * Generic Address Decode Windows bit settings
21 */
22#define TARGET_DEV_BUS 1
23#define TARGET_PCIE0 4
24#define TARGET_PCIE1 8
25#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
26#define ATTR_DEV_SPI_ROM 0x1f
27#define ATTR_DEV_BOOT 0x2f
28#define ATTR_DEV_CS3 0x37
29#define ATTR_DEV_CS2 0x3b
30#define ATTR_DEV_CS1 0x3d
31#define ATTR_DEV_CS0 0x3e
32#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l)))
33#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
34
35/*
36 * CPU Address Decode Windows registers
37 */
38#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
39#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
40
41static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
42{
43 /*
44 * Find the control register base address for this window.
45 *
46 * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
47 * MBUS bridge depending on which CPU core we're running on,
48 * so we don't need to take that into account here.
49 */
50
51 return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
52}
53
54/*
55 * Description of the windows needed by the platform code
56 */
57static struct orion_addr_map_cfg addr_map_cfg __initdata = {
58 .num_wins = 14,
59 .remappable_wins = 8,
60 .win_cfg_base = win_cfg_base,
61};
62
63void __init mv78xx0_setup_cpu_mbus(void)
64{
65 /*
66 * Disable, clear and configure windows.
67 */
68 orion_config_wins(&addr_map_cfg, NULL);
69
70 /*
71 * Setup MBUS dram target info.
72 */
73 if (mv78xx0_core_index() == 0)
74 orion_setup_cpu_mbus_target(&addr_map_cfg,
75 (void __iomem *) DDR_WINDOW_CPU0_BASE);
76 else
77 orion_setup_cpu_mbus_target(&addr_map_cfg,
78 (void __iomem *) DDR_WINDOW_CPU1_BASE);
79}
80
81void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
82 int maj, int min)
83{
84 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
85 TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
86}
87
88void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
89 int maj, int min)
90{
91 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
92 TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
93}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0efa14498ebc..749a7f8c4992 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -334,6 +334,14 @@ void __init mv78xx0_uart3_init(void)
334void __init mv78xx0_init_early(void) 334void __init mv78xx0_init_early(void)
335{ 335{
336 orion_time_set_base(TIMER_VIRT_BASE); 336 orion_time_set_base(TIMER_VIRT_BASE);
337 if (mv78xx0_core_index() == 0)
338 mvebu_mbus_init("marvell,mv78xx0-mbus",
339 BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
340 DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
341 else
342 mvebu_mbus_init("marvell,mv78xx0-mbus",
343 BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
344 DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
337} 345}
338 346
339void __init_refok mv78xx0_timer_init(void) 347void __init_refok mv78xx0_timer_init(void)
@@ -397,8 +405,6 @@ void __init mv78xx0_init(void)
397 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); 405 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
398 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); 406 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
399 407
400 mv78xx0_setup_cpu_mbus();
401
402#ifdef CONFIG_CACHE_FEROCEON_L2 408#ifdef CONFIG_CACHE_FEROCEON_L2
403 feroceon_l2_init(is_l2_writethrough()); 409 feroceon_l2_init(is_l2_writethrough());
404#endif 410#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 46200a183cf2..723748d8ba7d 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -60,13 +60,18 @@
60 */ 60 */
61#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) 61#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
62#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) 62#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
63#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
64#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
65#define BRIDGE_WINS_SZ (0xA000)
63 66
64/* 67/*
65 * Register Map 68 * Register Map
66 */ 69 */
67#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) 70#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
68#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) 71#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
69#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) 72#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
73#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
74#define DDR_WINDOW_CPU_SZ (0x20)
70 75
71#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) 76#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
72#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) 77#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index ee8c0b51df2c..dc26a654c496 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -10,11 +10,11 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/mbus.h>
13#include <video/vga.h> 14#include <video/vga.h>
14#include <asm/irq.h> 15#include <asm/irq.h>
15#include <asm/mach/pci.h> 16#include <asm/mach/pci.h>
16#include <plat/pcie.h> 17#include <plat/pcie.h>
17#include <plat/addr-map.h>
18#include <mach/mv78xx0.h> 18#include <mach/mv78xx0.h>
19#include "common.h" 19#include "common.h"
20 20
@@ -54,7 +54,6 @@ static void __init mv78xx0_pcie_preinit(void)
54 int i; 54 int i;
55 u32 size_each; 55 u32 size_each;
56 u32 start; 56 u32 start;
57 int win = 0;
58 57
59 pcie_io_space.name = "PCIe I/O Space"; 58 pcie_io_space.name = "PCIe I/O Space";
60 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); 59 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
@@ -72,6 +71,7 @@ static void __init mv78xx0_pcie_preinit(void)
72 start = MV78XX0_PCIE_MEM_PHYS_BASE; 71 start = MV78XX0_PCIE_MEM_PHYS_BASE;
73 for (i = 0; i < num_pcie_ports; i++) { 72 for (i = 0; i < num_pcie_ports; i++) {
74 struct pcie_port *pp = pcie_port + i; 73 struct pcie_port *pp = pcie_port + i;
74 char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
75 75
76 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 76 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
77 "PCIe %d.%d MEM", pp->maj, pp->min); 77 "PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,12 +85,17 @@ static void __init mv78xx0_pcie_preinit(void)
85 if (request_resource(&iomem_resource, &pp->res)) 85 if (request_resource(&iomem_resource, &pp->res))
86 panic("can't allocate PCIe MEM sub-space"); 86 panic("can't allocate PCIe MEM sub-space");
87 87
88 mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, 88 snprintf(winname, sizeof(winname), "pcie%d.%d",
89 resource_size(&pp->res), 89 pp->maj, pp->min);
90 pp->maj, pp->min); 90
91 91 mvebu_mbus_add_window_remap_flags(winname,
92 mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, 92 pp->res.start,
93 pp->maj, pp->min); 93 resource_size(&pp->res),
94 MVEBU_MBUS_NO_REMAP,
95 MVEBU_MBUS_PCI_MEM);
96 mvebu_mbus_add_window_remap_flags(winname,
97 i * SZ_64K, SZ_64K,
98 0, MVEBU_MBUS_PCI_IO);
94 } 99 }
95} 100}
96 101
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13ef1fed..e11acbb0a46d 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -13,6 +13,8 @@ config ARCH_MVEBU
13 select MVEBU_CLK_CORE 13 select MVEBU_CLK_CORE
14 select MVEBU_CLK_CPU 14 select MVEBU_CLK_CPU
15 select MVEBU_CLK_GATING 15 select MVEBU_CLK_GATING
16 select MVEBU_MBUS
17 select ZONE_DMA if ARM_LPAE
16 18
17if ARCH_MVEBU 19if ARCH_MVEBU
18 20
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index da93bcbc74c1..ba769e082ad4 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
5 5
6obj-y += system-controller.o 6obj-y += system-controller.o
7obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o 7obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
8obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o 8obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o
9obj-$(CONFIG_SMP) += platsmp.o headsmp.o 9obj-$(CONFIG_SMP) += platsmp.o headsmp.o
10obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 10obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
deleted file mode 100644
index ab9b3bd4fef5..000000000000
--- a/arch/arm/mach-mvebu/addr-map.c
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * Address map functions for Marvell 370 / XP SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mbus.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <plat/addr-map.h>
20
21/*
22 * Generic Address Decode Windows bit settings
23 */
24#define ARMADA_XP_TARGET_DEV_BUS 1
25#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
26#define ARMADA_XP_TARGET_ETH1 3
27#define ARMADA_XP_TARGET_PCIE_0_2 4
28#define ARMADA_XP_TARGET_ETH0 7
29#define ARMADA_XP_TARGET_PCIE_1_3 8
30
31#define ARMADA_370_TARGET_DEV_BUS 1
32#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
33#define ARMADA_370_TARGET_PCIE_0 4
34#define ARMADA_370_TARGET_PCIE_1 8
35
36#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
37#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
38
39static const struct __initdata orion_addr_map_info
40armada_xp_addr_map_info[] = {
41 /*
42 * Window for the BootROM, needed for SMP on Armada XP
43 */
44 { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
45 ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
46 /* End marker */
47 { -1, 0, 0, 0, 0, 0 },
48};
49
50static const struct __initdata orion_addr_map_info
51armada_370_addr_map_info[] = {
52 /* End marker */
53 { -1, 0, 0, 0, 0, 0 },
54};
55
56static struct of_device_id of_addr_decoding_controller_table[] = {
57 { .compatible = "marvell,armada-addr-decoding-controller" },
58 { /* end of list */ },
59};
60
61static void __iomem *
62armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
63{
64 unsigned int offset;
65
66 /* The register layout is a bit annoying and the below code
67 * tries to cope with it.
68 * - At offset 0x0, there are the registers for the first 8
69 * windows, with 4 registers of 32 bits per window (ctrl,
70 * base, remap low, remap high)
71 * - Then at offset 0x80, there is a hole of 0x10 bytes for
72 * the internal registers base address and internal units
73 * sync barrier register.
74 * - Then at offset 0x90, there the registers for 12
75 * windows, with only 2 registers of 32 bits per window
76 * (ctrl, base).
77 */
78 if (win < 8)
79 offset = (win << 4);
80 else
81 offset = ARMADA_WINDOW_8_PLUS_OFFSET + ((win - 8) << 3);
82
83 return cfg->bridge_virt_base + offset;
84}
85
86static struct __initdata orion_addr_map_cfg addr_map_cfg = {
87 .num_wins = 20,
88 .remappable_wins = 8,
89 .win_cfg_base = armada_cfg_base,
90};
91
92static int __init armada_setup_cpu_mbus(void)
93{
94 struct device_node *np;
95 void __iomem *mbus_unit_addr_decoding_base;
96 void __iomem *sdram_addr_decoding_base;
97
98 np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
99 if (!np)
100 return -ENODEV;
101
102 mbus_unit_addr_decoding_base = of_iomap(np, 0);
103 BUG_ON(!mbus_unit_addr_decoding_base);
104
105 sdram_addr_decoding_base =
106 mbus_unit_addr_decoding_base +
107 ARMADA_SDRAM_ADDR_DECODING_OFFSET;
108
109 addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
110
111 if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
112 addr_map_cfg.hw_io_coherency = 1;
113
114 /*
115 * Disable, clear and configure windows.
116 */
117 if (of_machine_is_compatible("marvell,armadaxp"))
118 orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
119 else if (of_machine_is_compatible("marvell,armada370"))
120 orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
121 else {
122 pr_err("Unsupported SoC\n");
123 return -EINVAL;
124 }
125
126 /*
127 * Setup MBUS dram target info.
128 */
129 orion_setup_cpu_mbus_target(&addr_map_cfg,
130 sdram_addr_decoding_base);
131 return 0;
132}
133
134/* Using a early_initcall is needed so that this initialization gets
135 * done before the SMP initialization, which requires the BootROM to
136 * be remapped. */
137early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index a5ea616d6d12..12d3655830d1 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -19,6 +19,7 @@
19#include <linux/time-armada-370-xp.h> 19#include <linux/time-armada-370-xp.h>
20#include <linux/clk/mvebu.h> 20#include <linux/clk/mvebu.h>
21#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
22#include <linux/mbus.h>
22#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
23#include <asm/mach/map.h> 24#include <asm/mach/map.h>
24#include <asm/mach/time.h> 25#include <asm/mach/time.h>
@@ -48,12 +49,29 @@ void __init armada_370_xp_timer_and_clk_init(void)
48 49
49void __init armada_370_xp_init_early(void) 50void __init armada_370_xp_init_early(void)
50{ 51{
52 char *mbus_soc_name;
53
51 /* 54 /*
52 * Some Armada 370/XP devices allocate their coherent buffers 55 * Some Armada 370/XP devices allocate their coherent buffers
53 * from atomic context. Increase size of atomic coherent pool 56 * from atomic context. Increase size of atomic coherent pool
54 * to make sure such the allocations won't fail. 57 * to make sure such the allocations won't fail.
55 */ 58 */
56 init_dma_coherent_pool_size(SZ_1M); 59 init_dma_coherent_pool_size(SZ_1M);
60
61 /*
62 * This initialization will be replaced by a DT-based
63 * initialization once the mvebu-mbus driver gains DT support.
64 */
65 if (of_machine_is_compatible("marvell,armada370"))
66 mbus_soc_name = "marvell,armada370-mbus";
67 else
68 mbus_soc_name = "marvell,armadaxp-mbus";
69
70 mvebu_mbus_init(mbus_soc_name,
71 ARMADA_370_XP_MBUS_WINS_BASE,
72 ARMADA_370_XP_MBUS_WINS_SIZE,
73 ARMADA_370_XP_SDRAM_WINS_BASE,
74 ARMADA_370_XP_SDRAM_WINS_SIZE);
57} 75}
58 76
59static void __init armada_370_xp_dt_init(void) 77static void __init armada_370_xp_dt_init(void)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index c6a7d74fddfe..2070e1b4f342 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,9 +16,15 @@
16#define __MACH_ARMADA_370_XP_H 16#define __MACH_ARMADA_370_XP_H
17 17
18#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 18#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
19#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000) 19#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000)
20#define ARMADA_370_XP_REGS_SIZE SZ_1M 20#define ARMADA_370_XP_REGS_SIZE SZ_1M
21 21
22/* These defines can go away once mvebu-mbus has a DT binding */
23#define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
24#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
25#define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
26#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
27
22#ifdef CONFIG_SMP 28#ifdef CONFIG_SMP
23#include <linux/cpumask.h> 29#include <linux/cpumask.h>
24 30
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index fe16aaf7c19c..875ea748391c 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/of.h> 23#include <linux/of.h>
24#include <linux/mbus.h>
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
25#include <asm/smp_plat.h> 26#include <asm/smp_plat.h>
26#include "common.h" 27#include "common.h"
@@ -109,6 +110,7 @@ void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
109 set_secondary_cpus_clock(); 110 set_secondary_cpus_clock();
110 flush_cache_all(); 111 flush_cache_all();
111 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); 112 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
113 mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
112} 114}
113 115
114struct smp_operations armada_xp_smp_ops __initdata = { 116struct smp_operations armada_xp_smp_ops __initdata = {
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9e809a7c05c0..45da805fb236 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,4 +1,4 @@
1obj-y += common.o addr-map.o pci.o irq.o mpp.o 1obj-y += common.o pci.o irq.o mpp.o
2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o 2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o 3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o 4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
deleted file mode 100644
index b5efc0fd31cb..000000000000
--- a/arch/arm/mach-orion5x/addr-map.c
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * arch/arm/mach-orion5x/addr-map.c
3 *
4 * Address map functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mbus.h>
16#include <linux/io.h>
17#include <mach/hardware.h>
18#include <plat/addr-map.h>
19#include "common.h"
20
21/*
22 * The Orion has fully programmable address map. There's a separate address
23 * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
24 * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
25 * address decode windows that allow it to access any of the Orion resources.
26 *
27 * CPU address decoding --
28 * Linux assumes that it is the boot loader that already setup the access to
29 * DDR and internal registers.
30 * Setup access to PCI and PCIe IO/MEM space is issued by this file.
31 * Setup access to various devices located on the device bus interface (e.g.
32 * flashes, RTC, etc) should be issued by machine-setup.c according to
33 * specific board population (by using orion5x_setup_*_win()).
34 *
35 * Non-CPU Masters address decoding --
36 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
37 * banks only (the typical use case).
38 * Setup access for each master to DDR is issued by platform device setup.
39 */
40
41/*
42 * Generic Address Decode Windows bit settings
43 */
44#define TARGET_DEV_BUS 1
45#define TARGET_PCI 3
46#define TARGET_PCIE 4
47#define TARGET_SRAM 9
48#define ATTR_PCIE_MEM 0x59
49#define ATTR_PCIE_IO 0x51
50#define ATTR_PCIE_WA 0x79
51#define ATTR_PCI_MEM 0x59
52#define ATTR_PCI_IO 0x51
53#define ATTR_DEV_CS0 0x1e
54#define ATTR_DEV_CS1 0x1d
55#define ATTR_DEV_CS2 0x1b
56#define ATTR_DEV_BOOT 0xf
57#define ATTR_SRAM 0x0
58
59static int __initdata win_alloc_count;
60
61static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
62 const int win)
63{
64 u32 dev, rev;
65
66 orion5x_pcie_id(&dev, &rev);
67 if ((dev == MV88F5281_DEV_ID && win < 4)
68 || (dev == MV88F5182_DEV_ID && win < 2)
69 || (dev == MV88F5181_DEV_ID && win < 2)
70 || (dev == MV88F6183_DEV_ID && win < 4))
71 return 1;
72
73 return 0;
74}
75
76/*
77 * Description of the windows needed by the platform code
78 */
79static struct orion_addr_map_cfg addr_map_cfg __initdata = {
80 .num_wins = 8,
81 .cpu_win_can_remap = cpu_win_can_remap,
82 .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
83};
84
85static const struct __initdata orion_addr_map_info addr_map_info[] = {
86 /*
87 * Setup windows for PCI+PCIe IO+MEM space.
88 */
89 { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
90 TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
91 },
92 { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
93 TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
94 },
95 { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
96 TARGET_PCIE, ATTR_PCIE_MEM, -1
97 },
98 { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
99 TARGET_PCI, ATTR_PCI_MEM, -1
100 },
101 /* End marker */
102 { -1, 0, 0, 0, 0, 0 }
103};
104
105void __init orion5x_setup_cpu_mbus_bridge(void)
106{
107 /*
108 * Disable, clear and configure windows.
109 */
110 orion_config_wins(&addr_map_cfg, addr_map_info);
111 win_alloc_count = 4;
112
113 /*
114 * Setup MBUS dram target info.
115 */
116 orion_setup_cpu_mbus_target(&addr_map_cfg,
117 (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
118}
119
120void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
121{
122 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
123 TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
124}
125
126void __init orion5x_setup_dev0_win(u32 base, u32 size)
127{
128 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
129 TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
130}
131
132void __init orion5x_setup_dev1_win(u32 base, u32 size)
133{
134 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
135 TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
136}
137
138void __init orion5x_setup_dev2_win(u32 base, u32 size)
139{
140 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
141 TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
142}
143
144void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
145{
146 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
147 TARGET_PCIE, ATTR_PCIE_WA, -1);
148}
149
150void __init orion5x_setup_sram_win(void)
151{
152 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
153 ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
154 TARGET_SRAM, ATTR_SRAM, -1);
155}
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index 35a8014529ca..6bbc8786c1e3 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -41,7 +41,7 @@ static void __init orion5x_dt_init(void)
41 /* 41 /*
42 * Setup Orion address map 42 * Setup Orion address map
43 */ 43 */
44 orion5x_setup_cpu_mbus_bridge(); 44 orion5x_setup_wins();
45 45
46 /* Setup root of clk tree */ 46 /* Setup root of clk tree */
47 clk_init(); 47 clk_init();
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index d068f1431c40..8e468e3a6015 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -34,7 +34,6 @@
34#include <linux/platform_data/usb-ehci-orion.h> 34#include <linux/platform_data/usb-ehci-orion.h>
35#include <plat/time.h> 35#include <plat/time.h>
36#include <plat/common.h> 36#include <plat/common.h>
37#include <plat/addr-map.h>
38#include "common.h" 37#include "common.h"
39 38
40/***************************************************************************** 39/*****************************************************************************
@@ -174,7 +173,8 @@ void __init orion5x_xor_init(void)
174 ****************************************************************************/ 173 ****************************************************************************/
175static void __init orion5x_crypto_init(void) 174static void __init orion5x_crypto_init(void)
176{ 175{
177 orion5x_setup_sram_win(); 176 mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
177 ORION5X_SRAM_SIZE);
178 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 178 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
179 SZ_8K, IRQ_ORION5X_CESA); 179 SZ_8K, IRQ_ORION5X_CESA);
180} 180}
@@ -193,6 +193,9 @@ void __init orion5x_wdt_init(void)
193 ****************************************************************************/ 193 ****************************************************************************/
194void __init orion5x_init_early(void) 194void __init orion5x_init_early(void)
195{ 195{
196 u32 rev, dev;
197 const char *mbus_soc_name;
198
196 orion_time_set_base(TIMER_VIRT_BASE); 199 orion_time_set_base(TIMER_VIRT_BASE);
197 200
198 /* 201 /*
@@ -201,6 +204,46 @@ void __init orion5x_init_early(void)
201 * the allocations won't fail. 204 * the allocations won't fail.
202 */ 205 */
203 init_dma_coherent_pool_size(SZ_1M); 206 init_dma_coherent_pool_size(SZ_1M);
207
208 /* Initialize the MBUS driver */
209 orion5x_pcie_id(&dev, &rev);
210 if (dev == MV88F5281_DEV_ID)
211 mbus_soc_name = "marvell,orion5x-88f5281-mbus";
212 else if (dev == MV88F5182_DEV_ID)
213 mbus_soc_name = "marvell,orion5x-88f5182-mbus";
214 else if (dev == MV88F5181_DEV_ID)
215 mbus_soc_name = "marvell,orion5x-88f5181-mbus";
216 else if (dev == MV88F6183_DEV_ID)
217 mbus_soc_name = "marvell,orion5x-88f6183-mbus";
218 else
219 mbus_soc_name = NULL;
220 mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
221 ORION5X_BRIDGE_WINS_SZ,
222 ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
223}
224
225void orion5x_setup_wins(void)
226{
227 /*
228 * The PCIe windows will no longer be statically allocated
229 * here once Orion5x is migrated to the pci-mvebu driver.
230 */
231 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
232 ORION5X_PCIE_IO_SIZE,
233 ORION5X_PCIE_IO_BUS_BASE,
234 MVEBU_MBUS_PCI_IO);
235 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
236 ORION5X_PCIE_MEM_SIZE,
237 MVEBU_MBUS_NO_REMAP,
238 MVEBU_MBUS_PCI_MEM);
239 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
240 ORION5X_PCI_IO_SIZE,
241 ORION5X_PCI_IO_BUS_BASE,
242 MVEBU_MBUS_PCI_IO);
243 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
244 ORION5X_PCI_MEM_SIZE,
245 MVEBU_MBUS_NO_REMAP,
246 MVEBU_MBUS_PCI_MEM);
204} 247}
205 248
206int orion5x_tclk; 249int orion5x_tclk;
@@ -282,7 +325,7 @@ void __init orion5x_init(void)
282 /* 325 /*
283 * Setup Orion address map 326 * Setup Orion address map
284 */ 327 */
285 orion5x_setup_cpu_mbus_bridge(); 328 orion5x_setup_wins();
286 329
287 /* Setup root of clk tree */ 330 /* Setup root of clk tree */
288 clk_init(); 331 clk_init();
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index e60345760283..cdaa01f3d186 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -17,18 +17,7 @@ void clk_init(void);
17extern int orion5x_tclk; 17extern int orion5x_tclk;
18extern void orion5x_timer_init(void); 18extern void orion5x_timer_init(void);
19 19
20/* 20void orion5x_setup_wins(void);
21 * Enumerations and functions for Orion windows mapping. Used by Orion core
22 * functions to map its interfaces and by the machine-setup to map its on-
23 * board devices. Details in /mach-orion/addr-map.c
24 */
25void orion5x_setup_cpu_mbus_bridge(void);
26void orion5x_setup_dev_boot_win(u32 base, u32 size);
27void orion5x_setup_dev0_win(u32 base, u32 size);
28void orion5x_setup_dev1_win(u32 base, u32 size);
29void orion5x_setup_dev2_win(u32 base, u32 size);
30void orion5x_setup_pcie_wa_win(u32 base, u32 size);
31void orion5x_setup_sram_win(void);
32 21
33void orion5x_ehci0_init(void); 22void orion5x_ehci0_init(void);
34void orion5x_ehci1_init(void); 23void orion5x_ehci1_init(void);
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 57d0af74874d..16c88bbabc98 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -317,8 +317,8 @@ static void __init d2net_init(void)
317 d2net_sata_power_init(); 317 d2net_sata_power_init();
318 orion5x_sata_init(&d2net_sata_data); 318 orion5x_sata_init(&d2net_sata_data);
319 319
320 orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE, 320 mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
321 D2NET_NOR_BOOT_SIZE); 321 D2NET_NOR_BOOT_SIZE);
322 platform_device_register(&d2net_nor_flash); 322 platform_device_register(&d2net_nor_flash);
323 323
324 platform_device_register(&d2net_gpio_buttons); 324 platform_device_register(&d2net_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 76665640087b..4e1263da38bb 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -340,16 +340,19 @@ static void __init db88f5281_init(void)
340 orion5x_uart0_init(); 340 orion5x_uart0_init();
341 orion5x_uart1_init(); 341 orion5x_uart1_init();
342 342
343 orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, 343 mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
344 DB88F5281_NOR_BOOT_SIZE); 344 DB88F5281_NOR_BOOT_SIZE);
345 platform_device_register(&db88f5281_boot_flash); 345 platform_device_register(&db88f5281_boot_flash);
346 346
347 orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); 347 mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
348 DB88F5281_7SEG_SIZE);
348 349
349 orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); 350 mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
351 DB88F5281_NOR_SIZE);
350 platform_device_register(&db88f5281_nor_flash); 352 platform_device_register(&db88f5281_nor_flash);
351 353
352 orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); 354 mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
355 DB88F5281_NAND_SIZE);
353 platform_device_register(&db88f5281_nand_flash); 356 platform_device_register(&db88f5281_nand_flash);
354 357
355 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); 358 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 6eb1732757fd..9e6baf581ed3 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -611,7 +611,8 @@ static void __init dns323_init(void)
611 /* setup flash mapping 611 /* setup flash mapping
612 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 612 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
613 */ 613 */
614 orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); 614 mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
615 DNS323_NOR_BOOT_SIZE);
615 platform_device_register(&dns323_nor_flash); 616 platform_device_register(&dns323_nor_flash);
616 617
617 /* Sort out LEDs, Buttons and i2c devices */ 618 /* Sort out LEDs, Buttons and i2c devices */
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index d675e727803d..147615510dd0 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -154,8 +154,8 @@ void __init edmini_v2_init(void)
154 orion5x_ehci0_init(); 154 orion5x_ehci0_init();
155 orion5x_eth_init(&edmini_v2_eth_data); 155 orion5x_eth_init(&edmini_v2_eth_data);
156 156
157 orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE, 157 mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
158 EDMINI_V2_NOR_BOOT_SIZE); 158 EDMINI_V2_NOR_BOOT_SIZE);
159 platform_device_register(&edmini_v2_nor_flash); 159 platform_device_register(&edmini_v2_nor_flash);
160 160
161 pr_notice("edmini_v2: USB device port, flash write and power-off " 161 pr_notice("edmini_v2: USB device port, flash write and power-off "
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index d265f5484a8e..b78ff3248868 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -66,8 +66,10 @@
66 * Orion Registers Map 66 * Orion Registers Map
67 ******************************************************************************/ 67 ******************************************************************************/
68 68
69#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000)
70#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500)
71#define ORION5X_DDR_WINS_SZ (0x10)
69#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) 72#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
70#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500)
71#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) 73#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
72#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) 74#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
73#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) 75#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
@@ -81,6 +83,8 @@
81 83
82#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) 84#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
83#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) 85#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
86#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE)
87#define ORION5X_BRIDGE_WINS_SZ (0x80)
84 88
85#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) 89#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
86 90
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index b98403526218..aae10e4a917c 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -359,13 +359,13 @@ static void __init kurobox_pro_init(void)
359 orion5x_uart1_init(); 359 orion5x_uart1_init();
360 orion5x_xor_init(); 360 orion5x_xor_init();
361 361
362 orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, 362 mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
363 KUROBOX_PRO_NOR_BOOT_SIZE); 363 KUROBOX_PRO_NOR_BOOT_SIZE);
364 platform_device_register(&kurobox_pro_nor_flash); 364 platform_device_register(&kurobox_pro_nor_flash);
365 365
366 if (machine_is_kurobox_pro()) { 366 if (machine_is_kurobox_pro()) {
367 orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, 367 mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
368 KUROBOX_PRO_NAND_SIZE); 368 KUROBOX_PRO_NAND_SIZE);
369 platform_device_register(&kurobox_pro_nand_flash); 369 platform_device_register(&kurobox_pro_nand_flash);
370 } 370 }
371 371
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 044da5b6a6ae..24f4e14e5893 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -294,8 +294,8 @@ static void __init lschl_init(void)
294 orion5x_uart0_init(); 294 orion5x_uart0_init();
295 orion5x_xor_init(); 295 orion5x_xor_init();
296 296
297 orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE, 297 mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
298 LSCHL_NOR_BOOT_SIZE); 298 LSCHL_NOR_BOOT_SIZE);
299 platform_device_register(&lschl_nor_flash); 299 platform_device_register(&lschl_nor_flash);
300 300
301 platform_device_register(&lschl_leds); 301 platform_device_register(&lschl_leds);
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index d49f93423f52..fc653bb41e78 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -243,8 +243,8 @@ static void __init ls_hgl_init(void)
243 orion5x_uart0_init(); 243 orion5x_uart0_init();
244 orion5x_xor_init(); 244 orion5x_xor_init();
245 245
246 orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE, 246 mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
247 LS_HGL_NOR_BOOT_SIZE); 247 LS_HGL_NOR_BOOT_SIZE);
248 platform_device_register(&ls_hgl_nor_flash); 248 platform_device_register(&ls_hgl_nor_flash);
249 249
250 platform_device_register(&ls_hgl_button_device); 250 platform_device_register(&ls_hgl_button_device);
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 8e3965c6c0fe..18e66e617dc2 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -244,8 +244,8 @@ static void __init lsmini_init(void)
244 orion5x_uart0_init(); 244 orion5x_uart0_init();
245 orion5x_xor_init(); 245 orion5x_xor_init();
246 246
247 orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE, 247 mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
248 LSMINI_NOR_BOOT_SIZE); 248 LSMINI_NOR_BOOT_SIZE);
249 platform_device_register(&lsmini_nor_flash); 249 platform_device_register(&lsmini_nor_flash);
250 250
251 platform_device_register(&lsmini_button_device); 251 platform_device_register(&lsmini_button_device);
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 0ec94a1f2b16..827acbafc9dc 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -241,7 +241,8 @@ static void __init mss2_init(void)
241 orion5x_uart0_init(); 241 orion5x_uart0_init();
242 orion5x_xor_init(); 242 orion5x_xor_init();
243 243
244 orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE); 244 mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
245 MSS2_NOR_BOOT_SIZE);
245 platform_device_register(&mss2_nor_flash); 246 platform_device_register(&mss2_nor_flash);
246 247
247 platform_device_register(&mss2_button_device); 248 platform_device_register(&mss2_button_device);
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 18143f2a9093..92600ae2b4b6 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -204,7 +204,8 @@ static void __init mv2120_init(void)
204 orion5x_uart0_init(); 204 orion5x_uart0_init();
205 orion5x_xor_init(); 205 orion5x_xor_init();
206 206
207 orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE); 207 mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
208 MV2120_NOR_BOOT_SIZE);
208 platform_device_register(&mv2120_nor_flash); 209 platform_device_register(&mv2120_nor_flash);
209 210
210 platform_device_register(&mv2120_button_device); 211 platform_device_register(&mv2120_button_device);
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 282e503b003e..dd0641a0d074 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -397,8 +397,8 @@ static void __init net2big_init(void)
397 net2big_sata_power_init(); 397 net2big_sata_power_init();
398 orion5x_sata_init(&net2big_sata_data); 398 orion5x_sata_init(&net2big_sata_data);
399 399
400 orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE, 400 mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
401 NET2BIG_NOR_BOOT_SIZE); 401 NET2BIG_NOR_BOOT_SIZE);
402 platform_device_register(&net2big_nor_flash); 402 platform_device_register(&net2big_nor_flash);
403 403
404 platform_device_register(&net2big_gpio_buttons); 404 platform_device_register(&net2big_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index d9c7c3bf0d9c..503368023bb1 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -157,8 +157,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n"); 159 "read transaction workaround\n");
160 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 160 mvebu_mbus_add_window_remap_flags("pcie0.0",
161 ORION5X_PCIE_WA_SIZE); 161 ORION5X_PCIE_WA_PHYS_BASE,
162 ORION5X_PCIE_WA_SIZE,
163 MVEBU_MBUS_NO_REMAP,
164 MVEBU_MBUS_PCI_WA);
162 pcie_ops.read = pcie_rd_conf_wa; 165 pcie_ops.read = pcie_rd_conf_wa;
163 } 166 }
164 167
@@ -402,8 +405,9 @@ static void __init orion5x_pci_master_slave_enable(void)
402 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 405 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
403} 406}
404 407
405static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 408static void __init orion5x_setup_pci_wins(void)
406{ 409{
410 const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
407 u32 win_enable; 411 u32 win_enable;
408 int bus; 412 int bus;
409 int i; 413 int i;
@@ -420,7 +424,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
420 bus = orion5x_pci_local_bus_nr(); 424 bus = orion5x_pci_local_bus_nr();
421 425
422 for (i = 0; i < dram->num_cs; i++) { 426 for (i = 0; i < dram->num_cs; i++) {
423 struct mbus_dram_window *cs = dram->cs + i; 427 const struct mbus_dram_window *cs = dram->cs + i;
424 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 428 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
425 u32 reg; 429 u32 reg;
426 u32 val; 430 u32 val;
@@ -467,7 +471,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
467 /* 471 /*
468 * Point PCI unit MBUS decode windows to DRAM space. 472 * Point PCI unit MBUS decode windows to DRAM space.
469 */ 473 */
470 orion5x_setup_pci_wins(&orion_mbus_dram_info); 474 orion5x_setup_pci_wins();
471 475
472 /* 476 /*
473 * Master + Slave enable 477 * Master + Slave enable
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index d6e72f672afb..1c4498bf650a 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -123,8 +123,8 @@ static void __init rd88f5181l_fxo_init(void)
123 orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); 123 orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
124 orion5x_uart0_init(); 124 orion5x_uart0_init();
125 125
126 orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE, 126 mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
127 RD88F5181L_FXO_NOR_BOOT_SIZE); 127 RD88F5181L_FXO_NOR_BOOT_SIZE);
128 platform_device_register(&rd88f5181l_fxo_nor_boot_flash); 128 platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
129} 129}
130 130
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c8b7913310e5..adabe34c4fc6 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -130,8 +130,8 @@ static void __init rd88f5181l_ge_init(void)
130 orion5x_i2c_init(); 130 orion5x_i2c_init();
131 orion5x_uart0_init(); 131 orion5x_uart0_init();
132 132
133 orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE, 133 mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
134 RD88F5181L_GE_NOR_BOOT_SIZE); 134 RD88F5181L_GE_NOR_BOOT_SIZE);
135 platform_device_register(&rd88f5181l_ge_nor_boot_flash); 135 platform_device_register(&rd88f5181l_ge_nor_boot_flash);
136 136
137 i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); 137 i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index f9e156725d7c..66e77ec91532 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -264,10 +264,11 @@ static void __init rd88f5182_init(void)
264 orion5x_uart0_init(); 264 orion5x_uart0_init();
265 orion5x_xor_init(); 265 orion5x_xor_init();
266 266
267 orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, 267 mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
268 RD88F5182_NOR_BOOT_SIZE); 268 RD88F5182_NOR_BOOT_SIZE);
269 269
270 orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); 270 mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
271 RD88F5182_NOR_SIZE);
271 platform_device_register(&rd88f5182_nor_flash); 272 platform_device_register(&rd88f5182_nor_flash);
272 platform_device_register(&rd88f5182_gpio_leds); 273 platform_device_register(&rd88f5182_gpio_leds);
273 274
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index acc0877ec1c9..a0bfa53e7556 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -329,8 +329,8 @@ static void __init tsp2_init(void)
329 /* 329 /*
330 * Configure peripherals. 330 * Configure peripherals.
331 */ 331 */
332 orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE, 332 mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
333 TSP2_NOR_BOOT_SIZE); 333 TSP2_NOR_BOOT_SIZE);
334 platform_device_register(&tsp2_nor_flash); 334 platform_device_register(&tsp2_nor_flash);
335 335
336 orion5x_ehci0_init(); 336 orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9c17f0c2b488..80174f0f168e 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -286,8 +286,8 @@ static void __init qnap_ts209_init(void)
286 /* 286 /*
287 * Configure peripherals. 287 * Configure peripherals.
288 */ 288 */
289 orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, 289 mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
290 QNAP_TS209_NOR_BOOT_SIZE); 290 QNAP_TS209_NOR_BOOT_SIZE);
291 platform_device_register(&qnap_ts209_nor_flash); 291 platform_device_register(&qnap_ts209_nor_flash);
292 292
293 orion5x_ehci0_init(); 293 orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 8cc5ab6c503e..92592790d6da 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -277,8 +277,8 @@ static void __init qnap_ts409_init(void)
277 /* 277 /*
278 * Configure peripherals. 278 * Configure peripherals.
279 */ 279 */
280 orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, 280 mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
281 QNAP_TS409_NOR_BOOT_SIZE); 281 QNAP_TS409_NOR_BOOT_SIZE);
282 platform_device_register(&qnap_ts409_nor_flash); 282 platform_device_register(&qnap_ts409_nor_flash);
283 283
284 orion5x_ehci0_init(); 284 orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 66552ca7e05d..6b84863c018d 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -127,8 +127,8 @@ static void __init wnr854t_init(void)
127 orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); 127 orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
128 orion5x_uart0_init(); 128 orion5x_uart0_init();
129 129
130 orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE, 130 mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
131 WNR854T_NOR_BOOT_SIZE); 131 WNR854T_NOR_BOOT_SIZE);
132 platform_device_register(&wnr854t_nor_flash); 132 platform_device_register(&wnr854t_nor_flash);
133} 133}
134 134
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 2c5408e2e689..fae684bc54f2 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -213,8 +213,8 @@ static void __init wrt350n_v2_init(void)
213 orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); 213 orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
214 orion5x_uart0_init(); 214 orion5x_uart0_init();
215 215
216 orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE, 216 mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
217 WRT350N_V2_NOR_BOOT_SIZE); 217 WRT350N_V2_NOR_BOOT_SIZE);
218 platform_device_register(&wrt350n_v2_nor_flash); 218 platform_device_register(&wrt350n_v2_nor_flash);
219 platform_device_register(&wrt350n_v2_leds); 219 platform_device_register(&wrt350n_v2_leds);
220 platform_device_register(&wrt350n_v2_button_device); 220 platform_device_register(&wrt350n_v2_button_device);
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index a82cecb84948..2eca54b65906 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -3,8 +3,6 @@
3# 3#
4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include 4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
5 5
6obj-y += addr-map.o
7
8orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o 6orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
9obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o 7obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
10obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y) 8obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
deleted file mode 100644
index 807ac8e5cbc0..000000000000
--- a/arch/arm/plat-orion/addr-map.c
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * arch/arm/plat-orion/addr-map.c
3 *
4 * Address map functions for Marvell Orion based SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/mbus.h>
15#include <linux/io.h>
16#include <plat/addr-map.h>
17
18struct mbus_dram_target_info orion_mbus_dram_info;
19
20const struct mbus_dram_target_info *mv_mbus_dram_info(void)
21{
22 return &orion_mbus_dram_info;
23}
24EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
25
26/*
27 * DDR target is the same on all Orion platforms.
28 */
29#define TARGET_DDR 0
30
31/*
32 * Helpers to get DDR bank info
33 */
34#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
35#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
36
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL_OFF 0x0000
41#define WIN_BASE_OFF 0x0004
42#define WIN_REMAP_LO_OFF 0x0008
43#define WIN_REMAP_HI_OFF 0x000c
44
45#define ATTR_HW_COHERENCY (0x1 << 4)
46
47/*
48 * Default implementation
49 */
50static void __init __iomem *
51orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
52{
53 return cfg->bridge_virt_base + (win << 4);
54}
55
56/*
57 * Default implementation
58 */
59static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
60 const int win)
61{
62 if (win < cfg->remappable_wins)
63 return 1;
64
65 return 0;
66}
67
68void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
69 const int win, const u32 base,
70 const u32 size, const u8 target,
71 const u8 attr, const int remap)
72{
73 void __iomem *addr = cfg->win_cfg_base(cfg, win);
74 u32 ctrl, base_high, remap_addr;
75
76 if (win >= cfg->num_wins) {
77 printk(KERN_ERR "setup_cpu_win: trying to allocate window "
78 "%d when only %d allowed\n", win, cfg->num_wins);
79 }
80
81 base_high = base & 0xffff0000;
82 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
83
84 writel(base_high, addr + WIN_BASE_OFF);
85 writel(ctrl, addr + WIN_CTRL_OFF);
86 if (cfg->cpu_win_can_remap(cfg, win)) {
87 if (remap < 0)
88 remap_addr = base;
89 else
90 remap_addr = remap;
91 writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
92 writel(0, addr + WIN_REMAP_HI_OFF);
93 }
94}
95
96/*
97 * Configure a number of windows.
98 */
99static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
100 const struct orion_addr_map_info *info)
101{
102 while (info->win != -1) {
103 orion_setup_cpu_win(cfg, info->win, info->base, info->size,
104 info->target, info->attr, info->remap);
105 info++;
106 }
107}
108
109static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
110{
111 void __iomem *addr;
112 int i;
113
114 for (i = 0; i < cfg->num_wins; i++) {
115 addr = cfg->win_cfg_base(cfg, i);
116
117 writel(0, addr + WIN_BASE_OFF);
118 writel(0, addr + WIN_CTRL_OFF);
119 if (cfg->cpu_win_can_remap(cfg, i)) {
120 writel(0, addr + WIN_REMAP_LO_OFF);
121 writel(0, addr + WIN_REMAP_HI_OFF);
122 }
123 }
124}
125
126/*
127 * Disable, clear and configure windows.
128 */
129void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
130 const struct orion_addr_map_info *info)
131{
132 if (!cfg->cpu_win_can_remap)
133 cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
134
135 if (!cfg->win_cfg_base)
136 cfg->win_cfg_base = orion_win_cfg_base;
137
138 orion_disable_wins(cfg);
139
140 if (info)
141 orion_setup_cpu_wins(cfg, info);
142}
143
144/*
145 * Setup MBUS dram target info.
146 */
147void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
148 const void __iomem *ddr_window_cpu_base)
149{
150 int i;
151 int cs;
152
153 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
154
155 for (i = 0, cs = 0; i < 4; i++) {
156 u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
157 u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
158
159 /*
160 * We only take care of entries for which the chip
161 * select is enabled, and that don't have high base
162 * address bits set (devices can only access the first
163 * 32 bits of the memory).
164 */
165 if ((size & 1) && !(base & 0xF)) {
166 struct mbus_dram_window *w;
167
168 w = &orion_mbus_dram_info.cs[cs++];
169 w->cs_index = i;
170 w->mbus_attr = 0xf & ~(1 << i);
171 if (cfg->hw_io_coherency)
172 w->mbus_attr |= ATTR_HW_COHERENCY;
173 w->base = base & 0xffff0000;
174 w->size = (size | 0x0000ffff) + 1;
175 }
176 }
177 orion_mbus_dram_info.num_cs = cs;
178}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index c29ee7ea200b..e39c2ba6e2fb 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -439,6 +439,64 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
439 } 439 }
440} 440}
441 441
442#ifdef CONFIG_DEBUG_FS
443#include <linux/seq_file.h>
444
445static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
446{
447 struct orion_gpio_chip *ochip =
448 container_of(chip, struct orion_gpio_chip, chip);
449 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
450 int i;
451
452 out = readl_relaxed(GPIO_OUT(ochip));
453 io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
454 blink = readl_relaxed(GPIO_BLINK_EN(ochip));
455 in_pol = readl_relaxed(GPIO_IN_POL(ochip));
456 data_in = readl_relaxed(GPIO_DATA_IN(ochip));
457 cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
458 edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
459 lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
460
461 for (i = 0; i < chip->ngpio; i++) {
462 const char *label;
463 u32 msk;
464 bool is_out;
465
466 label = gpiochip_is_requested(chip, i);
467 if (!label)
468 continue;
469
470 msk = 1 << i;
471 is_out = !(io_conf & msk);
472
473 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
474
475 if (is_out) {
476 seq_printf(s, " out %s %s\n",
477 out & msk ? "hi" : "lo",
478 blink & msk ? "(blink )" : "");
479 continue;
480 }
481
482 seq_printf(s, " in %s (act %s) - IRQ",
483 (data_in ^ in_pol) & msk ? "hi" : "lo",
484 in_pol & msk ? "lo" : "hi");
485 if (!((edg_msk | lvl_msk) & msk)) {
486 seq_printf(s, " disabled\n");
487 continue;
488 }
489 if (edg_msk & msk)
490 seq_printf(s, " edge ");
491 if (lvl_msk & msk)
492 seq_printf(s, " level");
493 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
494 }
495}
496#else
497#define orion_gpio_dbg_show NULL
498#endif
499
442void __init orion_gpio_init(struct device_node *np, 500void __init orion_gpio_init(struct device_node *np,
443 int gpio_base, int ngpio, 501 int gpio_base, int ngpio,
444 void __iomem *base, int mask_offset, 502 void __iomem *base, int mask_offset,
@@ -471,6 +529,7 @@ void __init orion_gpio_init(struct device_node *np,
471#ifdef CONFIG_OF 529#ifdef CONFIG_OF
472 ochip->chip.of_node = np; 530 ochip->chip.of_node = np;
473#endif 531#endif
532 ochip->chip.dbg_show = orion_gpio_dbg_show;
474 533
475 spin_lock_init(&ochip->lock); 534 spin_lock_init(&ochip->lock);
476 ochip->base = (void __iomem *)base; 535 ochip->base = (void __iomem *)base;
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index f20a321088a2..8b8c06d2e9c4 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base)
120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
121 * WIN[0-3] -> DRAM bank[0-3] 121 * WIN[0-3] -> DRAM bank[0-3]
122 */ 122 */
123static void __init orion_pcie_setup_wins(void __iomem *base, 123static void __init orion_pcie_setup_wins(void __iomem *base)
124 struct mbus_dram_target_info *dram)
125{ 124{
125 const struct mbus_dram_target_info *dram;
126 u32 size; 126 u32 size;
127 int i; 127 int i;
128 128
129 dram = mv_mbus_dram_info();
130
129 /* 131 /*
130 * First, disable and clear BARs and windows. 132 * First, disable and clear BARs and windows.
131 */ 133 */
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
150 */ 152 */
151 size = 0; 153 size = 0;
152 for (i = 0; i < dram->num_cs; i++) { 154 for (i = 0; i < dram->num_cs; i++) {
153 struct mbus_dram_window *cs = dram->cs + i; 155 const struct mbus_dram_window *cs = dram->cs + i;
154 156
155 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); 157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
156 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); 158 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base)
184 /* 186 /*
185 * Point PCIe unit MBUS decode windows to DRAM space. 187 * Point PCIe unit MBUS decode windows to DRAM space.
186 */ 188 */
187 orion_pcie_setup_wins(base, &orion_mbus_dram_info); 189 orion_pcie_setup_wins(base);
188 190
189 /* 191 /*
190 * Master + slave enable. 192 * Master + slave enable.
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 0f51ed687dc8..b05ecab915c4 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,13 @@
4 4
5menu "Bus devices" 5menu "Bus devices"
6 6
7config MVEBU_MBUS
8 bool
9 depends on PLAT_ORION
10 help
11 Driver needed for the MBus configuration on Marvell EBU SoCs
12 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
13
7config OMAP_OCP2SCP 14config OMAP_OCP2SCP
8 tristate "OMAP OCP2SCP DRIVER" 15 tristate "OMAP OCP2SCP DRIVER"
9 depends on ARCH_OMAP2PLUS 16 depends on ARCH_OMAP2PLUS
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 45d997c85453..3c7b53c12091 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
2# Makefile for the bus drivers. 2# Makefile for the bus drivers.
3# 3#
4 4
5obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
5obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o 6obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
6 7
7# Interconnect bus driver for OMAP SoCs. 8# Interconnect bus driver for OMAP SoCs.
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
new file mode 100644
index 000000000000..8740f46b4d0d
--- /dev/null
+++ b/drivers/bus/mvebu-mbus.c
@@ -0,0 +1,870 @@
1/*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window(),
39 * mvebu_mbus_add_window_remap_flags() and
40 * mvebu_mbus_del_window(). Since the (target, attribute) values
41 * differ from one SoC family to another, the API uses a 'const char
42 * *' string to identify devices, and this driver is responsible for
43 * knowing the mapping between the name of a device and its
44 * corresponding (target, attribute) in the current SoC family.
45 *
46 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
47 * see the list of CPU -> SDRAM windows and their configuration
48 * (file 'sdram') and the list of CPU -> devices windows and their
49 * configuration (file 'devices').
50 */
51
52#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/init.h>
55#include <linux/mbus.h>
56#include <linux/io.h>
57#include <linux/ioport.h>
58#include <linux/of.h>
59#include <linux/of_address.h>
60#include <linux/debugfs.h>
61
62/*
63 * DDR target is the same on all platforms.
64 */
65#define TARGET_DDR 0
66
67/*
68 * CPU Address Decode Windows registers
69 */
70#define WIN_CTRL_OFF 0x0000
71#define WIN_CTRL_ENABLE BIT(0)
72#define WIN_CTRL_TGT_MASK 0xf0
73#define WIN_CTRL_TGT_SHIFT 4
74#define WIN_CTRL_ATTR_MASK 0xff00
75#define WIN_CTRL_ATTR_SHIFT 8
76#define WIN_CTRL_SIZE_MASK 0xffff0000
77#define WIN_CTRL_SIZE_SHIFT 16
78#define WIN_BASE_OFF 0x0004
79#define WIN_BASE_LOW 0xffff0000
80#define WIN_BASE_HIGH 0xf
81#define WIN_REMAP_LO_OFF 0x0008
82#define WIN_REMAP_LOW 0xffff0000
83#define WIN_REMAP_HI_OFF 0x000c
84
85#define ATTR_HW_COHERENCY (0x1 << 4)
86
87#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
88#define DDR_BASE_CS_HIGH_MASK 0xf
89#define DDR_BASE_CS_LOW_MASK 0xff000000
90#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
91#define DDR_SIZE_ENABLED BIT(0)
92#define DDR_SIZE_CS_MASK 0x1c
93#define DDR_SIZE_CS_SHIFT 2
94#define DDR_SIZE_MASK 0xff000000
95
96#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
97
98struct mvebu_mbus_mapping {
99 const char *name;
100 u8 target;
101 u8 attr;
102 u8 attrmask;
103};
104
105/*
106 * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
107 * allow to get the real attribute value, discarding the special bits
108 * used to select a PCI MEM region or a PCI WA region. This allows the
109 * debugfs code to reverse-match the name of a device from its
110 * target/attr values.
111 *
112 * For all devices except PCI, all bits of 'attr' must be
113 * considered. For most SoCs, only bit 3 should be ignored (it allows
114 * to select between PCI MEM and PCI I/O). On Orion5x however, there
115 * is the special bit 5 to select a PCI WA region.
116 */
117#define MAPDEF_NOMASK 0xff
118#define MAPDEF_PCIMASK 0xf7
119#define MAPDEF_ORIONPCIMASK 0xd7
120
121/* Macro used to define one mvebu_mbus_mapping entry */
122#define MAPDEF(__n, __t, __a, __m) \
123 { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
124
125struct mvebu_mbus_state;
126
127struct mvebu_mbus_soc_data {
128 unsigned int num_wins;
129 unsigned int num_remappable_wins;
130 unsigned int (*win_cfg_offset)(const int win);
131 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
132 int (*show_cpu_target)(struct mvebu_mbus_state *s,
133 struct seq_file *seq, void *v);
134 const struct mvebu_mbus_mapping *map;
135};
136
137struct mvebu_mbus_state {
138 void __iomem *mbuswins_base;
139 void __iomem *sdramwins_base;
140 struct dentry *debugfs_root;
141 struct dentry *debugfs_sdram;
142 struct dentry *debugfs_devs;
143 const struct mvebu_mbus_soc_data *soc;
144 int hw_io_coherency;
145};
146
147static struct mvebu_mbus_state mbus_state;
148
149static struct mbus_dram_target_info mvebu_mbus_dram_info;
150const struct mbus_dram_target_info *mv_mbus_dram_info(void)
151{
152 return &mvebu_mbus_dram_info;
153}
154EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
155
156/*
157 * Functions to manipulate the address decoding windows
158 */
159
160static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
161 int win, int *enabled, u64 *base,
162 u32 *size, u8 *target, u8 *attr,
163 u64 *remap)
164{
165 void __iomem *addr = mbus->mbuswins_base +
166 mbus->soc->win_cfg_offset(win);
167 u32 basereg = readl(addr + WIN_BASE_OFF);
168 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
169
170 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
171 *enabled = 0;
172 return;
173 }
174
175 *enabled = 1;
176 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
177 *base |= (basereg & WIN_BASE_LOW);
178 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
179
180 if (target)
181 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
182
183 if (attr)
184 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
185
186 if (remap) {
187 if (win < mbus->soc->num_remappable_wins) {
188 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
189 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
190 *remap = ((u64)remap_hi << 32) | remap_low;
191 } else
192 *remap = 0;
193 }
194}
195
196static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
197 int win)
198{
199 void __iomem *addr;
200
201 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
202
203 writel(0, addr + WIN_BASE_OFF);
204 writel(0, addr + WIN_CTRL_OFF);
205 if (win < mbus->soc->num_remappable_wins) {
206 writel(0, addr + WIN_REMAP_LO_OFF);
207 writel(0, addr + WIN_REMAP_HI_OFF);
208 }
209}
210
211/* Checks whether the given window number is available */
212static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
213 const int win)
214{
215 void __iomem *addr = mbus->mbuswins_base +
216 mbus->soc->win_cfg_offset(win);
217 u32 ctrl = readl(addr + WIN_CTRL_OFF);
218 return !(ctrl & WIN_CTRL_ENABLE);
219}
220
221/*
222 * Checks whether the given (base, base+size) area doesn't overlap an
223 * existing region
224 */
225static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
226 phys_addr_t base, size_t size,
227 u8 target, u8 attr)
228{
229 u64 end = (u64)base + size;
230 int win;
231
232 for (win = 0; win < mbus->soc->num_wins; win++) {
233 u64 wbase, wend;
234 u32 wsize;
235 u8 wtarget, wattr;
236 int enabled;
237
238 mvebu_mbus_read_window(mbus, win,
239 &enabled, &wbase, &wsize,
240 &wtarget, &wattr, NULL);
241
242 if (!enabled)
243 continue;
244
245 wend = wbase + wsize;
246
247 /*
248 * Check if the current window overlaps with the
249 * proposed physical range
250 */
251 if ((u64)base < wend && end > wbase)
252 return 0;
253
254 /*
255 * Check if target/attribute conflicts
256 */
257 if (target == wtarget && attr == wattr)
258 return 0;
259 }
260
261 return 1;
262}
263
264static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
265 phys_addr_t base, size_t size)
266{
267 int win;
268
269 for (win = 0; win < mbus->soc->num_wins; win++) {
270 u64 wbase;
271 u32 wsize;
272 int enabled;
273
274 mvebu_mbus_read_window(mbus, win,
275 &enabled, &wbase, &wsize,
276 NULL, NULL, NULL);
277
278 if (!enabled)
279 continue;
280
281 if (base == wbase && size == wsize)
282 return win;
283 }
284
285 return -ENODEV;
286}
287
288static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
289 int win, phys_addr_t base, size_t size,
290 phys_addr_t remap, u8 target,
291 u8 attr)
292{
293 void __iomem *addr = mbus->mbuswins_base +
294 mbus->soc->win_cfg_offset(win);
295 u32 ctrl, remap_addr;
296
297 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
298 (attr << WIN_CTRL_ATTR_SHIFT) |
299 (target << WIN_CTRL_TGT_SHIFT) |
300 WIN_CTRL_ENABLE;
301
302 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
303 writel(ctrl, addr + WIN_CTRL_OFF);
304 if (win < mbus->soc->num_remappable_wins) {
305 if (remap == MVEBU_MBUS_NO_REMAP)
306 remap_addr = base;
307 else
308 remap_addr = remap;
309 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
310 writel(0, addr + WIN_REMAP_HI_OFF);
311 }
312
313 return 0;
314}
315
316static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
317 phys_addr_t base, size_t size,
318 phys_addr_t remap, u8 target,
319 u8 attr)
320{
321 int win;
322
323 if (remap == MVEBU_MBUS_NO_REMAP) {
324 for (win = mbus->soc->num_remappable_wins;
325 win < mbus->soc->num_wins; win++)
326 if (mvebu_mbus_window_is_free(mbus, win))
327 return mvebu_mbus_setup_window(mbus, win, base,
328 size, remap,
329 target, attr);
330 }
331
332
333 for (win = 0; win < mbus->soc->num_wins; win++)
334 if (mvebu_mbus_window_is_free(mbus, win))
335 return mvebu_mbus_setup_window(mbus, win, base, size,
336 remap, target, attr);
337
338 return -ENOMEM;
339}
340
341/*
342 * Debugfs debugging
343 */
344
345/* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
346static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
347 struct seq_file *seq, void *v)
348{
349 int i;
350
351 for (i = 0; i < 4; i++) {
352 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
353 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
354 u64 base;
355 u32 size;
356
357 if (!(sizereg & DDR_SIZE_ENABLED)) {
358 seq_printf(seq, "[%d] disabled\n", i);
359 continue;
360 }
361
362 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
363 base |= basereg & DDR_BASE_CS_LOW_MASK;
364 size = (sizereg | ~DDR_SIZE_MASK);
365
366 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
367 i, (unsigned long long)base,
368 (unsigned long long)base + size + 1,
369 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
370 }
371
372 return 0;
373}
374
375/* Special function for Dove */
376static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
377 struct seq_file *seq, void *v)
378{
379 int i;
380
381 for (i = 0; i < 2; i++) {
382 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
383 u64 base;
384 u32 size;
385
386 if (!(map & 1)) {
387 seq_printf(seq, "[%d] disabled\n", i);
388 continue;
389 }
390
391 base = map & 0xff800000;
392 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
393
394 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
395 i, (unsigned long long)base,
396 (unsigned long long)base + size, i);
397 }
398
399 return 0;
400}
401
402static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
403{
404 struct mvebu_mbus_state *mbus = &mbus_state;
405 return mbus->soc->show_cpu_target(mbus, seq, v);
406}
407
408static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
409{
410 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
411}
412
413static const struct file_operations mvebu_sdram_debug_fops = {
414 .open = mvebu_sdram_debug_open,
415 .read = seq_read,
416 .llseek = seq_lseek,
417 .release = single_release,
418};
419
420static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
421{
422 struct mvebu_mbus_state *mbus = &mbus_state;
423 int win;
424
425 for (win = 0; win < mbus->soc->num_wins; win++) {
426 u64 wbase, wremap;
427 u32 wsize;
428 u8 wtarget, wattr;
429 int enabled, i;
430 const char *name;
431
432 mvebu_mbus_read_window(mbus, win,
433 &enabled, &wbase, &wsize,
434 &wtarget, &wattr, &wremap);
435
436 if (!enabled) {
437 seq_printf(seq, "[%02d] disabled\n", win);
438 continue;
439 }
440
441
442 for (i = 0; mbus->soc->map[i].name; i++)
443 if (mbus->soc->map[i].target == wtarget &&
444 mbus->soc->map[i].attr ==
445 (wattr & mbus->soc->map[i].attrmask))
446 break;
447
448 name = mbus->soc->map[i].name ?: "unknown";
449
450 seq_printf(seq, "[%02d] %016llx - %016llx : %s",
451 win, (unsigned long long)wbase,
452 (unsigned long long)(wbase + wsize), name);
453
454 if (win < mbus->soc->num_remappable_wins) {
455 seq_printf(seq, " (remap %016llx)\n",
456 (unsigned long long)wremap);
457 } else
458 seq_printf(seq, "\n");
459 }
460
461 return 0;
462}
463
464static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
465{
466 return single_open(file, mvebu_devs_debug_show, inode->i_private);
467}
468
469static const struct file_operations mvebu_devs_debug_fops = {
470 .open = mvebu_devs_debug_open,
471 .read = seq_read,
472 .llseek = seq_lseek,
473 .release = single_release,
474};
475
476/*
477 * SoC-specific functions and definitions
478 */
479
480static unsigned int orion_mbus_win_offset(int win)
481{
482 return win << 4;
483}
484
485static unsigned int armada_370_xp_mbus_win_offset(int win)
486{
487 /* The register layout is a bit annoying and the below code
488 * tries to cope with it.
489 * - At offset 0x0, there are the registers for the first 8
490 * windows, with 4 registers of 32 bits per window (ctrl,
491 * base, remap low, remap high)
492 * - Then at offset 0x80, there is a hole of 0x10 bytes for
493 * the internal registers base address and internal units
494 * sync barrier register.
495 * - Then at offset 0x90, there the registers for 12
496 * windows, with only 2 registers of 32 bits per window
497 * (ctrl, base).
498 */
499 if (win < 8)
500 return win << 4;
501 else
502 return 0x90 + ((win - 8) << 3);
503}
504
505static unsigned int mv78xx0_mbus_win_offset(int win)
506{
507 if (win < 8)
508 return win << 4;
509 else
510 return 0x900 + ((win - 8) << 4);
511}
512
513static void __init
514mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
515{
516 int i;
517 int cs;
518
519 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
520
521 for (i = 0, cs = 0; i < 4; i++) {
522 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
523 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
524
525 /*
526 * We only take care of entries for which the chip
527 * select is enabled, and that don't have high base
528 * address bits set (devices can only access the first
529 * 32 bits of the memory).
530 */
531 if ((size & DDR_SIZE_ENABLED) &&
532 !(base & DDR_BASE_CS_HIGH_MASK)) {
533 struct mbus_dram_window *w;
534
535 w = &mvebu_mbus_dram_info.cs[cs++];
536 w->cs_index = i;
537 w->mbus_attr = 0xf & ~(1 << i);
538 if (mbus->hw_io_coherency)
539 w->mbus_attr |= ATTR_HW_COHERENCY;
540 w->base = base & DDR_BASE_CS_LOW_MASK;
541 w->size = (size | ~DDR_SIZE_MASK) + 1;
542 }
543 }
544 mvebu_mbus_dram_info.num_cs = cs;
545}
546
547static void __init
548mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
549{
550 int i;
551 int cs;
552
553 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
554
555 for (i = 0, cs = 0; i < 2; i++) {
556 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
557
558 /*
559 * Chip select enabled?
560 */
561 if (map & 1) {
562 struct mbus_dram_window *w;
563
564 w = &mvebu_mbus_dram_info.cs[cs++];
565 w->cs_index = i;
566 w->mbus_attr = 0; /* CS address decoding done inside */
567 /* the DDR controller, no need to */
568 /* provide attributes */
569 w->base = map & 0xff800000;
570 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
571 }
572 }
573
574 mvebu_mbus_dram_info.num_cs = cs;
575}
576
577static const struct mvebu_mbus_mapping armada_370_map[] = {
578 MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
579 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
580 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
581 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
582 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
583 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
584 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
585 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
586 {},
587};
588
589static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
590 .num_wins = 20,
591 .num_remappable_wins = 8,
592 .win_cfg_offset = armada_370_xp_mbus_win_offset,
593 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
594 .show_cpu_target = mvebu_sdram_debug_show_orion,
595 .map = armada_370_map,
596};
597
598static const struct mvebu_mbus_mapping armada_xp_map[] = {
599 MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
600 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
601 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
602 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
603 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
604 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
605 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
606 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
607 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
608 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
609 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
610 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
611 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
612 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
613 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
614 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
615 {},
616};
617
618static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
619 .num_wins = 20,
620 .num_remappable_wins = 8,
621 .win_cfg_offset = armada_370_xp_mbus_win_offset,
622 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
623 .show_cpu_target = mvebu_sdram_debug_show_orion,
624 .map = armada_xp_map,
625};
626
627static const struct mvebu_mbus_mapping kirkwood_map[] = {
628 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
629 MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
630 MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
631 MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
632 {},
633};
634
635static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
636 .num_wins = 8,
637 .num_remappable_wins = 4,
638 .win_cfg_offset = orion_mbus_win_offset,
639 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
640 .show_cpu_target = mvebu_sdram_debug_show_orion,
641 .map = kirkwood_map,
642};
643
644static const struct mvebu_mbus_mapping dove_map[] = {
645 MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
646 MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
647 MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
648 MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
649 MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
650 {},
651};
652
653static const struct mvebu_mbus_soc_data dove_mbus_data = {
654 .num_wins = 8,
655 .num_remappable_wins = 4,
656 .win_cfg_offset = orion_mbus_win_offset,
657 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
658 .show_cpu_target = mvebu_sdram_debug_show_dove,
659 .map = dove_map,
660};
661
662static const struct mvebu_mbus_mapping orion5x_map[] = {
663 MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
664 MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
665 MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
666 MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
667 MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
668 MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
669 MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
670 {},
671};
672
673/*
674 * Some variants of Orion5x have 4 remappable windows, some other have
675 * only two of them.
676 */
677static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
678 .num_wins = 8,
679 .num_remappable_wins = 4,
680 .win_cfg_offset = orion_mbus_win_offset,
681 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
682 .show_cpu_target = mvebu_sdram_debug_show_orion,
683 .map = orion5x_map,
684};
685
686static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
687 .num_wins = 8,
688 .num_remappable_wins = 2,
689 .win_cfg_offset = orion_mbus_win_offset,
690 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
691 .show_cpu_target = mvebu_sdram_debug_show_orion,
692 .map = orion5x_map,
693};
694
695static const struct mvebu_mbus_mapping mv78xx0_map[] = {
696 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
697 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
698 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
699 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
700 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
701 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
702 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
703 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
704 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
705 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
706 {},
707};
708
709static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
710 .num_wins = 14,
711 .num_remappable_wins = 8,
712 .win_cfg_offset = mv78xx0_mbus_win_offset,
713 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
714 .show_cpu_target = mvebu_sdram_debug_show_orion,
715 .map = mv78xx0_map,
716};
717
718/*
719 * The driver doesn't yet have a DT binding because the details of
720 * this DT binding still need to be sorted out. However, as a
721 * preparation, we already use of_device_id to match a SoC description
722 * string against the SoC specific details of this driver.
723 */
724static const struct of_device_id of_mvebu_mbus_ids[] = {
725 { .compatible = "marvell,armada370-mbus",
726 .data = &armada_370_mbus_data, },
727 { .compatible = "marvell,armadaxp-mbus",
728 .data = &armada_xp_mbus_data, },
729 { .compatible = "marvell,kirkwood-mbus",
730 .data = &kirkwood_mbus_data, },
731 { .compatible = "marvell,dove-mbus",
732 .data = &dove_mbus_data, },
733 { .compatible = "marvell,orion5x-88f5281-mbus",
734 .data = &orion5x_4win_mbus_data, },
735 { .compatible = "marvell,orion5x-88f5182-mbus",
736 .data = &orion5x_2win_mbus_data, },
737 { .compatible = "marvell,orion5x-88f5181-mbus",
738 .data = &orion5x_2win_mbus_data, },
739 { .compatible = "marvell,orion5x-88f6183-mbus",
740 .data = &orion5x_4win_mbus_data, },
741 { .compatible = "marvell,mv78xx0-mbus",
742 .data = &mv78xx0_mbus_data, },
743 { },
744};
745
746/*
747 * Public API of the driver
748 */
749int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
750 size_t size, phys_addr_t remap,
751 unsigned int flags)
752{
753 struct mvebu_mbus_state *s = &mbus_state;
754 u8 target, attr;
755 int i;
756
757 if (!s->soc->map)
758 return -ENODEV;
759
760 for (i = 0; s->soc->map[i].name; i++)
761 if (!strcmp(s->soc->map[i].name, devname))
762 break;
763
764 if (!s->soc->map[i].name) {
765 pr_err("mvebu-mbus: unknown device '%s'\n", devname);
766 return -ENODEV;
767 }
768
769 target = s->soc->map[i].target;
770 attr = s->soc->map[i].attr;
771
772 if (flags == MVEBU_MBUS_PCI_MEM)
773 attr |= 0x8;
774 else if (flags == MVEBU_MBUS_PCI_WA)
775 attr |= 0x28;
776
777 if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
778 pr_err("mvebu-mbus: cannot add window '%s', conflicts with another window\n",
779 devname);
780 return -EINVAL;
781 }
782
783 return mvebu_mbus_alloc_window(s, base, size, remap, target, attr);
784
785}
786
787int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
788{
789 return mvebu_mbus_add_window_remap_flags(devname, base, size,
790 MVEBU_MBUS_NO_REMAP, 0);
791}
792
793int mvebu_mbus_del_window(phys_addr_t base, size_t size)
794{
795 int win;
796
797 win = mvebu_mbus_find_window(&mbus_state, base, size);
798 if (win < 0)
799 return win;
800
801 mvebu_mbus_disable_window(&mbus_state, win);
802 return 0;
803}
804
805static __init int mvebu_mbus_debugfs_init(void)
806{
807 struct mvebu_mbus_state *s = &mbus_state;
808
809 /*
810 * If no base has been initialized, doesn't make sense to
811 * register the debugfs entries. We may be on a multiplatform
812 * kernel that isn't running a Marvell EBU SoC.
813 */
814 if (!s->mbuswins_base)
815 return 0;
816
817 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
818 if (s->debugfs_root) {
819 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
820 s->debugfs_root, NULL,
821 &mvebu_sdram_debug_fops);
822 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
823 s->debugfs_root, NULL,
824 &mvebu_devs_debug_fops);
825 }
826
827 return 0;
828}
829fs_initcall(mvebu_mbus_debugfs_init);
830
831int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
832 size_t mbuswins_size,
833 phys_addr_t sdramwins_phys_base,
834 size_t sdramwins_size)
835{
836 struct mvebu_mbus_state *mbus = &mbus_state;
837 const struct of_device_id *of_id;
838 int win;
839
840 for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
841 if (!strcmp(of_id->compatible, soc))
842 break;
843
844 if (!of_id->compatible) {
845 pr_err("mvebu-mbus: could not find a matching SoC family\n");
846 return -ENODEV;
847 }
848
849 mbus->soc = of_id->data;
850
851 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
852 if (!mbus->mbuswins_base)
853 return -ENOMEM;
854
855 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
856 if (!mbus->sdramwins_base) {
857 iounmap(mbus_state.mbuswins_base);
858 return -ENOMEM;
859 }
860
861 if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
862 mbus->hw_io_coherency = 1;
863
864 for (win = 0; win < mbus->soc->num_wins; win++)
865 mvebu_mbus_disable_window(mbus, win);
866
867 mbus->soc->setup_cpu_target(mbus);
868
869 return 0;
870}
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index efa1a6d7aca8..dba482e31a13 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -32,6 +32,20 @@ struct mbus_dram_target_info
32 } cs[4]; 32 } cs[4];
33}; 33};
34 34
35/* Flags for PCI/PCIe address decoding regions */
36#define MVEBU_MBUS_PCI_IO 0x1
37#define MVEBU_MBUS_PCI_MEM 0x2
38#define MVEBU_MBUS_PCI_WA 0x3
39
40/*
41 * Magic value that explicits that we don't need a remapping-capable
42 * address decoding window.
43 */
44#define MVEBU_MBUS_NO_REMAP (0xffffffff)
45
46/* Maximum size of a mbus window name */
47#define MVEBU_MBUS_MAX_WINNAME_SZ 32
48
35/* 49/*
36 * The Marvell mbus is to be found only on SOCs from the Orion family 50 * The Marvell mbus is to be found only on SOCs from the Orion family
37 * at the moment. Provide a dummy stub for other architectures. 51 * at the moment. Provide a dummy stub for other architectures.
@@ -44,4 +58,15 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
44 return NULL; 58 return NULL;
45} 59}
46#endif 60#endif
47#endif 61
62int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
63 size_t size, phys_addr_t remap,
64 unsigned int flags);
65int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
66 size_t size);
67int mvebu_mbus_del_window(phys_addr_t base, size_t size);
68int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
69 size_t mbus_size, phys_addr_t sdram_phys_base,
70 size_t sdram_size);
71
72#endif /* __LINUX_MBUS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-08 01:16:25 -0400