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authorAlex Deucher <alexander.deucher@amd.com>2012-03-20 17:18:18 -0400
committerDave Airlie <airlied@redhat.com>2012-03-21 02:55:53 -0400
commit8b074dd64053d0bf93eed0638b74a8fec401577f (patch)
treea1bee9e80ca26770b6a858760872f2225d1c9ae3
parent0f0de06c809eac783ddb4ddfc52c9db43af94b4f (diff)
drm/radeon/kms: add support for MC ucode loading on SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/si.c195
-rw-r--r--drivers/gpu/drm/radeon/sid.h16
2 files changed, 211 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 0938c21e792d..a8789de8e6db 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -77,6 +77,201 @@ int si_get_temp(struct radeon_device *rdev)
77 return actual_temp; 77 return actual_temp;
78} 78}
79 79
80#define TAHITI_IO_MC_REGS_SIZE 36
81
82static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
83 {0x0000006f, 0x03044000},
84 {0x00000070, 0x0480c018},
85 {0x00000071, 0x00000040},
86 {0x00000072, 0x01000000},
87 {0x00000074, 0x000000ff},
88 {0x00000075, 0x00143400},
89 {0x00000076, 0x08ec0800},
90 {0x00000077, 0x040000cc},
91 {0x00000079, 0x00000000},
92 {0x0000007a, 0x21000409},
93 {0x0000007c, 0x00000000},
94 {0x0000007d, 0xe8000000},
95 {0x0000007e, 0x044408a8},
96 {0x0000007f, 0x00000003},
97 {0x00000080, 0x00000000},
98 {0x00000081, 0x01000000},
99 {0x00000082, 0x02000000},
100 {0x00000083, 0x00000000},
101 {0x00000084, 0xe3f3e4f4},
102 {0x00000085, 0x00052024},
103 {0x00000087, 0x00000000},
104 {0x00000088, 0x66036603},
105 {0x00000089, 0x01000000},
106 {0x0000008b, 0x1c0a0000},
107 {0x0000008c, 0xff010000},
108 {0x0000008e, 0xffffefff},
109 {0x0000008f, 0xfff3efff},
110 {0x00000090, 0xfff3efbf},
111 {0x00000094, 0x00101101},
112 {0x00000095, 0x00000fff},
113 {0x00000096, 0x00116fff},
114 {0x00000097, 0x60010000},
115 {0x00000098, 0x10010000},
116 {0x00000099, 0x00006000},
117 {0x0000009a, 0x00001000},
118 {0x0000009f, 0x00a77400}
119};
120
121static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
122 {0x0000006f, 0x03044000},
123 {0x00000070, 0x0480c018},
124 {0x00000071, 0x00000040},
125 {0x00000072, 0x01000000},
126 {0x00000074, 0x000000ff},
127 {0x00000075, 0x00143400},
128 {0x00000076, 0x08ec0800},
129 {0x00000077, 0x040000cc},
130 {0x00000079, 0x00000000},
131 {0x0000007a, 0x21000409},
132 {0x0000007c, 0x00000000},
133 {0x0000007d, 0xe8000000},
134 {0x0000007e, 0x044408a8},
135 {0x0000007f, 0x00000003},
136 {0x00000080, 0x00000000},
137 {0x00000081, 0x01000000},
138 {0x00000082, 0x02000000},
139 {0x00000083, 0x00000000},
140 {0x00000084, 0xe3f3e4f4},
141 {0x00000085, 0x00052024},
142 {0x00000087, 0x00000000},
143 {0x00000088, 0x66036603},
144 {0x00000089, 0x01000000},
145 {0x0000008b, 0x1c0a0000},
146 {0x0000008c, 0xff010000},
147 {0x0000008e, 0xffffefff},
148 {0x0000008f, 0xfff3efff},
149 {0x00000090, 0xfff3efbf},
150 {0x00000094, 0x00101101},
151 {0x00000095, 0x00000fff},
152 {0x00000096, 0x00116fff},
153 {0x00000097, 0x60010000},
154 {0x00000098, 0x10010000},
155 {0x00000099, 0x00006000},
156 {0x0000009a, 0x00001000},
157 {0x0000009f, 0x00a47400}
158};
159
160static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
161 {0x0000006f, 0x03044000},
162 {0x00000070, 0x0480c018},
163 {0x00000071, 0x00000040},
164 {0x00000072, 0x01000000},
165 {0x00000074, 0x000000ff},
166 {0x00000075, 0x00143400},
167 {0x00000076, 0x08ec0800},
168 {0x00000077, 0x040000cc},
169 {0x00000079, 0x00000000},
170 {0x0000007a, 0x21000409},
171 {0x0000007c, 0x00000000},
172 {0x0000007d, 0xe8000000},
173 {0x0000007e, 0x044408a8},
174 {0x0000007f, 0x00000003},
175 {0x00000080, 0x00000000},
176 {0x00000081, 0x01000000},
177 {0x00000082, 0x02000000},
178 {0x00000083, 0x00000000},
179 {0x00000084, 0xe3f3e4f4},
180 {0x00000085, 0x00052024},
181 {0x00000087, 0x00000000},
182 {0x00000088, 0x66036603},
183 {0x00000089, 0x01000000},
184 {0x0000008b, 0x1c0a0000},
185 {0x0000008c, 0xff010000},
186 {0x0000008e, 0xffffefff},
187 {0x0000008f, 0xfff3efff},
188 {0x00000090, 0xfff3efbf},
189 {0x00000094, 0x00101101},
190 {0x00000095, 0x00000fff},
191 {0x00000096, 0x00116fff},
192 {0x00000097, 0x60010000},
193 {0x00000098, 0x10010000},
194 {0x00000099, 0x00006000},
195 {0x0000009a, 0x00001000},
196 {0x0000009f, 0x00a37400}
197};
198
199/* ucode loading */
200static int si_mc_load_microcode(struct radeon_device *rdev)
201{
202 const __be32 *fw_data;
203 u32 running, blackout = 0;
204 u32 *io_mc_regs;
205 int i, ucode_size, regs_size;
206
207 if (!rdev->mc_fw)
208 return -EINVAL;
209
210 switch (rdev->family) {
211 case CHIP_TAHITI:
212 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
213 ucode_size = SI_MC_UCODE_SIZE;
214 regs_size = TAHITI_IO_MC_REGS_SIZE;
215 break;
216 case CHIP_PITCAIRN:
217 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
218 ucode_size = SI_MC_UCODE_SIZE;
219 regs_size = TAHITI_IO_MC_REGS_SIZE;
220 break;
221 case CHIP_VERDE:
222 default:
223 io_mc_regs = (u32 *)&verde_io_mc_regs;
224 ucode_size = SI_MC_UCODE_SIZE;
225 regs_size = TAHITI_IO_MC_REGS_SIZE;
226 break;
227 }
228
229 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
230
231 if (running == 0) {
232 if (running) {
233 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
234 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
235 }
236
237 /* reset the engine and set to writable */
238 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
239 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
240
241 /* load mc io regs */
242 for (i = 0; i < regs_size; i++) {
243 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
244 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
245 }
246 /* load the MC ucode */
247 fw_data = (const __be32 *)rdev->mc_fw->data;
248 for (i = 0; i < ucode_size; i++)
249 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
250
251 /* put the engine back into the active state */
252 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
253 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
254 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
255
256 /* wait for training to complete */
257 for (i = 0; i < rdev->usec_timeout; i++) {
258 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
259 break;
260 udelay(1);
261 }
262 for (i = 0; i < rdev->usec_timeout; i++) {
263 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
264 break;
265 udelay(1);
266 }
267
268 if (running)
269 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);