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authorXie Xiaobo <X.Xie@freescale.com>2013-11-06 04:08:03 -0500
committerScott Wood <scottwood@freescale.com>2014-01-07 20:09:29 -0500
commit8a6be2bdb608dec6b988d2b9a875a88f8b684bfb (patch)
tree6eccf86fc900bfe9a4d983001cf711434d4ab535
parent72c916ae97ff503b01fa21efe91d4328439ab004 (diff)
powerpc/85xx: Add TWR-P1025 board support
TWR-P1025 Overview ----------------- 512Mbyte DDR3 (on board DDR) 64MB Nor Flash eTSEC1: Connected to RGMII PHY AR8035 eTSEC3: Connected to RGMII PHY AR8035 Two USB2.0 Type A One microSD Card slot One mini-PCIe slot One mini-USB TypeB dual UART Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [scottwood@freescale.com: use pr_info rather than KERN_INFO] Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/video/ssd1289fb.txt13
-rw-r--r--arch/powerpc/boot/dts/p1025twr.dts95
-rw-r--r--arch/powerpc/boot/dts/p1025twr.dtsi280
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig6
-rw-r--r--arch/powerpc/platforms/85xx/Makefile1
-rw-r--r--arch/powerpc/platforms/85xx/twr_p102x.c147
6 files changed, 542 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/video/ssd1289fb.txt b/Documentation/devicetree/bindings/video/ssd1289fb.txt
new file mode 100644
index 000000000000..4fcd5e68cb6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ssd1289fb.txt
@@ -0,0 +1,13 @@
1* Solomon SSD1289 Framebuffer Driver
2
3Required properties:
4 - compatible: Should be "solomon,ssd1289fb". The only supported bus for
5 now is lbc.
6 - reg: Should contain address of the controller on the LBC bus. The detail
7 was described in Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
8
9Examples:
10display@2,0 {
11 compatible = "solomon,ssd1289fb";
12 reg = <0x2 0x0000 0x0004>;
13};
diff --git a/arch/powerpc/boot/dts/p1025twr.dts b/arch/powerpc/boot/dts/p1025twr.dts
new file mode 100644
index 000000000000..9036a4987905
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dts
@@ -0,0 +1,95 @@
1/*
2 * P1025 TWR Device Tree Source (32-bit address map)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1025";
38 compatible = "fsl,TWR-P1025";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR Flash and SSD1289 */
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x2 0x0 0x0 0xe0000000 0x00020000>;
50 };
51
52 soc: soc@ffe00000 {
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@ffe09000 {
57 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xa0000000
62 0x2000000 0x0 0xa0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@ffe0a000 {
72 reg = <0 0xffe0a000 0 0x1000>;
73 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
74 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0x80000000
77 0x2000000 0x0 0x80000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 qe: qe@ffe80000 {
87 ranges = <0x0 0x0 0xffe80000 0x40000>;
88 reg = <0 0xffe80000 0 0x480>;
89 brg-frequency = <0>;
90 bus-frequency = <0>;
91 };
92};
93
94/include/ "p1025twr.dtsi"
95/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000000000000..8453501c256e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,280 @@
1/*
2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/{
36 aliases {
37 ethernet3 = &enet3;
38 ethernet4 = &enet4;
39 };
40};
41
42&lbc {
43 nor@0,0 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
47 reg = <0x0 0x0 0x4000000>;
48 bank-width = <2>;
49 device-width = <1>;
50
51 partition@0 {
52 /* This location must not be altered */
53 /* 256KB for Vitesse 7385 Switch firmware */
54 reg = <0x0 0x00040000>;
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
57 };
58
59 partition@40000 {
60 /* 256KB for DTB Image */
61 reg = <0x00040000 0x00040000>;
62 label = "NOR DTB Image";
63 };
64
65 partition@80000 {
66 /* 5.5 MB for Linux Kernel Image */
67 reg = <0x00080000 0x00580000>;
68 label = "NOR Linux Kernel Image";
69 };
70
71 partition@400000 {
72 /* 56.75MB for Root file System */
73 reg = <0x00600000 0x038c0000>;
74 label = "NOR Root File System";
75 };
76
77 partition@ec0000 {
78 /* This location must not be altered */
79 /* 256KB for QE ucode firmware*/
80 reg = <0x03ec0000 0x00040000>;
81 label = "NOR QE microcode firmware";
82 read-only;
83 };
84
85 partition@f00000 {
86 /* This location must not be altered */
87 /* 512KB for u-boot Bootloader Image */
88 /* 512KB for u-boot Environment Variables */
89 reg = <0x03f00000 0x00100000>;
90 label = "NOR U-Boot Image";
91 read-only;
92 };
93 };
94
95 /* CS2 for Display */
96 display@2,0 {
97 compatible = "solomon,ssd1289fb";
98 reg = <0x2 0x0000 0x0004>;
99 };
100
101};
102
103&soc {
104 usb@22000 {
105 phy_type = "ulpi";
106 };
107
108 mdio@24000 {
109 phy0: ethernet-phy@2 {
110 interrupt-parent = <&mpic>;
111 interrupts = <1 1 0 0>;
112 reg = <0x2>;
113 };
114
115 phy1: ethernet-phy@1 {
116 interrupt-parent = <&mpic>;
117 interrupts = <2 1 0 0>;
118 reg = <0x1>;
119 };
120
121 tbi0: tbi-phy@11 {
122 reg = <0x11>;
123 device_type = "tbi-phy";
124 };
125 };
126
127 mdio@25000 {
128 tbi1: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133
134 mdio@26000 {
135 tbi2: tbi-phy@11 {
136 reg = <0x11>;
137 device_type = "tbi-phy";
138 };
139 };
140
141 enet0: ethernet@b0000 {
142 phy-handle = <&phy0>;
143 phy-connection-type = "rgmii-id";
144
145 };
146
147 enet1: ethernet@b1000 {
148 status = "disabled";
149 };
150
151 enet2: ethernet@b2000 {
152 phy-handle = <&phy1>;
153 phy-connection-type = "rgmii-id";
154 };
155
156 par_io@e0100 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 reg = <0xe0100 0x60>;
160 ranges = <0x0 0xe0100 0x60>;
161 device_type = "par_io";
162 num-ports = <3>;
163 pio1: ucc_pin@01 {
164 pio-map = <
165 /* port pin dir open_drain assignment has_irq */
166 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
167 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
168 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
169 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
170 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
171 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
172 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
173 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
174 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
175 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
176 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
177 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
178 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
179 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
180 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
181 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
182 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
183 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
184 };
185
186 pio2: ucc_pin@02 {
187 pio-map = <
188 /* port pin dir open_drain assignment has_irq */
189 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
190 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
191 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
192 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
193 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
194 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
195 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
196 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
197 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
198 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
199 };
200
201 pio3: ucc_pin@03 {
202 pio-map = <
203 /* port pin dir open_drain assignment has_irq */
204 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
205 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
206 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
207 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
208 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
209 };
210
211 pio4: ucc_pin@04 {
212 pio-map = <
213 /* port pin dir open_drain assignment has_irq */
214 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
215 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
216 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
217 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
218 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
219 };
220 };
221};
222
223&qe {
224 enet3: ucc@2000 {
225 device_type = "network";
226 compatible = "ucc_geth";
227 rx-clock-name = "clk12";
228 tx-clock-name = "clk9";
229 pio-handle = <&pio1>;
230 phy-handle = <&qe_phy0>;
231 phy-connection-type = "mii";
232 };
233
234 mdio@2120 {
235 qe_phy0: ethernet-phy@18 {
236 interrupt-parent = <&mpic>;
237 interrupts = <4 1 0 0>;
238 reg = <0x18>;
239 device_type = "ethernet-phy";
240 };
241 qe_phy1: ethernet-phy@19 {
242 interrupt-parent = <&mpic>;
243 interrupts = <5 1 0 0>;
244 reg = <0x19>;
245 device_type = "ethernet-phy";
246 };
247 tbi-phy@11 {
248 reg = <0x11>;
249 device_type = "tbi-phy";
250 };
251 };
252
253 enet4: ucc@2400 {
254 device_type = "network";
255 compatible = "ucc_geth";
256 rx-clock-name = "none";
257 tx-clock-name = "clk13";
258 pio-handle = <&pio2>;
259 phy-handle = <&qe_phy1>;
260 phy-connection-type = "rmii";
261 };
262
263 serial2: ucc@2600 {
264 device_type = "serial";
265 compatible = "ucc_uart";
266 port-number = <0>;
267 rx-clock-name = "brg6";
268 tx-clock-name = "brg6";
269 pio-handle = <&pio3>;
270 };
271
272 serial3: ucc@2200 {
273 device_type = "serial";
274 compatible = "ucc_uart";
275 port-number = <1>;
276 rx-clock-name = "brg2";
277 tx-clock-name = "brg2";
278 pio-handle = <&pio4>;
279 };
280};
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 4d4634958cfb..c17aae80e7ff 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -123,6 +123,12 @@ config P1023_RDS
123 help 123 help
124 This option enables support for the P1023 RDS and RDB boards 124 This option enables support for the P1023 RDS and RDB boards
125 125
126config TWR_P102x
127 bool "Freescale TWR-P102x"
128 select DEFAULT_UIMAGE
129 help
130 This option enables support for the TWR-P1025 board.
131
126config SOCRATES 132config SOCRATES
127 bool "Socrates" 133 bool "Socrates"
128 select DEFAULT_UIMAGE 134 select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index dd4c0b59577b..25cebe74ac46 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
18obj-$(CONFIG_P1022_DS) += p1022_ds.o 18obj-$(CONFIG_P1022_DS) += p1022_ds.o
19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o 19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
20obj-$(CONFIG_P1023_RDS) += p1023_rds.o 20obj-$(CONFIG_P1023_RDS) += p1023_rds.o
21obj-$(CONFIG_TWR_P102x) += twr_p102x.o
21obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o 22obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
22obj-$(CONFIG_STX_GP3) += stx_gp3.o 23obj-$(CONFIG_STX_GP3) += stx_gp3.o
23obj-$(CONFIG_TQM85xx) += tqm85xx.o 24obj-$(CONFIG_TQM85xx) += tqm85xx.o
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
new file mode 100644
index 000000000000..c25ff10f05ee
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -0,0 +1,147 @@
1/*
2 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Michael Johnston <michael.johnston@freescale.com>
5 *
6 * Description:
7 * TWR-P102x Board Setup
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/of_platform.h>
20
21#include <asm/pci-bridge.h>
22#include <asm/udbg.h>
23#include <asm/mpic.h>
24#include <asm/qe.h>
25#include <asm/qe_ic.h>
26#include <asm/fsl_guts.h>
27
28#include <sysdev/fsl_soc.h>
29#include <sysdev/fsl_pci.h>
30#include "smp.h"
31
32#include "mpc85xx.h"
33
34static void __init twr_p1025_pic_init(void)
35{
36 struct mpic *mpic;
37
38#ifdef CONFIG_QUICC_ENGINE
39 struct device_node *np;
40#endif
41
42 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
43 MPIC_SINGLE_DEST_CPU,
44 0, 256, " OpenPIC ");
45
46 BUG_ON(mpic == NULL);
47 mpic_init(mpic);
48
49#ifdef CONFIG_QUICC_ENGINE
50 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
51 if (np) {
52 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
53 qe_ic_cascade_high_mpic);
54 of_node_put(np);
55 } else
56 pr_err("Could not find qe-ic node\n");
57#endif
58}
59
60/* ************************************************************************
61 *
62 * Setup the architecture
63 *
64 */
65static void __init twr_p1025_setup_arch(void)
66{
67#ifdef CONFIG_QUICC_ENGINE
68 struct device_node *np;
69#endif
70
71 if (ppc_md.progress)
72 ppc_md.progress("twr_p1025_setup_arch()", 0);
73
74 mpc85xx_smp_init();
75
76 fsl_pci_assign_primary();
77
78#ifdef CONFIG_QUICC_ENGINE
79 mpc85xx_qe_init();
80
81#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
82 if (machine_is(twr_p1025)) {
83 struct ccsr_guts __iomem *guts;
84
85 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
86 if (np) {
87 guts = of_iomap(np, 0);
88 if (!guts)
89 pr_err("twr_p1025: could not map global utilities register\n");
90 else {
91 /* P1025 has pins muxed for QE and other functions. To
92 * enable QE UEC mode, we need to set bit QE0 for UCC1
93 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
94 * and QE12 for QE MII management signals in PMUXCR
95 * register.
96 * Set QE mux bits in PMUXCR */
97 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
98 MPC85xx_PMUXCR_QE(3) |
99 MPC85xx_PMUXCR_QE(9) |
100 MPC85xx_PMUXCR_QE(12));
101 iounmap(guts);
102
103#if defined(CONFIG_SERIAL_QE)
104 /* On P1025TWR board, the UCC7 acted as UART port.
105 * However, The UCC7's CTS pin is low level in default,
106 * it will impact the transmission in full duplex
107 * communication. So disable the Flow control pin PA18.
108 * The UCC7 UART just can use RXD and TXD pins.
109 */
110 par_io_config_pin(0, 18, 0, 0, 0, 0);
111#endif
112 /* Drive PB29 to CPLD low - CPLD will then change
113 * muxing from LBC to QE */
114 par_io_config_pin(1, 29, 1, 0, 0, 0);
115 par_io_data_set(1, 29, 0);
116 }
117 of_node_put(np);
118 }
119 }
120#endif
121#endif /* CONFIG_QUICC_ENGINE */
122
123 pr_info("TWR-P1025 board from Freescale Semiconductor\n");
124}
125
126machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
127
128static int __init twr_p1025_probe(void)
129{
130 unsigned long root = of_get_flat_dt_root();
131
132 return of_flat_dt_is_compatible(root, "fsl,TWR-P1025");
133}
134
135define_machine(twr_p1025) {
136 .name = "TWR-P1025",
137 .probe = twr_p1025_probe,
138 .setup_arch = twr_p1025_setup_arch,
139 .init_IRQ = twr_p1025_pic_init,
140#ifdef CONFIG_PCI
141 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
142#endif
143 .get_irq = mpic_get_irq,
144 .restart = fsl_rstcr_restart,
145 .calibrate_decr = generic_calibrate_decr,
146 .progress = udbg_progress,
147};
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-31 01:33:39 -0400