drm/radeon: programm the VCE fw BAR as well

Otherwise the VCE firmware needs to be in the first 256MB of VRAM.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index c648e1996dab..243a36c93b8f 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -2129,6 +2129,7 @@
 #define VCE_UENC_REG_CLOCK_GATING       0x207c0
 #define VCE_SYS_INT_EN                  0x21300
 #       define VCE_SYS_INT_TRAP_INTERRUPT_EN    (1 << 3)
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR    0x2145c
 #define VCE_LMI_CTRL2                   0x21474
 #define VCE_LMI_CTRL                    0x21498
 #define VCE_LMI_VM_CTRL                 0x214a0
diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c
index 1ac7bb825a1b..fbbe78fbd087 100644
--- a/drivers/gpu/drm/radeon/vce_v2_0.c
+++ b/drivers/gpu/drm/radeon/vce_v2_0.c
@@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev)
         WREG32(VCE_LMI_SWAP_CNTL1, 0);
         WREG32(VCE_LMI_VM_CTRL, 0);
 
+        WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
+
+        addr &= 0xff;
         size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
         WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
         WREG32(VCE_VCPU_CACHE_SIZE0, size);