diff options
author | Christian König <christian.koenig@amd.com> | 2015-03-23 06:33:00 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2015-03-27 10:17:44 -0400 |
commit | 88f9eae4d74c1b5c35adb026d7f0d4d44d2fdf70 (patch) | |
tree | 9b934180db70f89728c61245b497a30b1894c787 | |
parent | 1b01fc347ae7d2b76ac849f7040a32582cb5aee3 (diff) |
drm/radeon: programm the VCE fw BAR as well
Otherwise the VCE firmware needs to be in the first 256MB of VRAM.
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/cikd.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/vce_v2_0.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index c648e1996dab..243a36c93b8f 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h | |||
@@ -2129,6 +2129,7 @@ | |||
2129 | #define VCE_UENC_REG_CLOCK_GATING 0x207c0 | 2129 | #define VCE_UENC_REG_CLOCK_GATING 0x207c0 |
2130 | #define VCE_SYS_INT_EN 0x21300 | 2130 | #define VCE_SYS_INT_EN 0x21300 |
2131 | # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) | 2131 | # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) |
2132 | #define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c | ||
2132 | #define VCE_LMI_CTRL2 0x21474 | 2133 | #define VCE_LMI_CTRL2 0x21474 |
2133 | #define VCE_LMI_CTRL 0x21498 | 2134 | #define VCE_LMI_CTRL 0x21498 |
2134 | #define VCE_LMI_VM_CTRL 0x214a0 | 2135 | #define VCE_LMI_VM_CTRL 0x214a0 |
diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c index 1ac7bb825a1b..fbbe78fbd087 100644 --- a/drivers/gpu/drm/radeon/vce_v2_0.c +++ b/drivers/gpu/drm/radeon/vce_v2_0.c | |||
@@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev) | |||
156 | WREG32(VCE_LMI_SWAP_CNTL1, 0); | 156 | WREG32(VCE_LMI_SWAP_CNTL1, 0); |
157 | WREG32(VCE_LMI_VM_CTRL, 0); | 157 | WREG32(VCE_LMI_VM_CTRL, 0); |
158 | 158 | ||
159 | WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8); | ||
160 | |||
161 | addr &= 0xff; | ||
159 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); | 162 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); |
160 | WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); | 163 | WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); |
161 | WREG32(VCE_VCPU_CACHE_SIZE0, size); | 164 | WREG32(VCE_VCPU_CACHE_SIZE0, size); |