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authorChris Wilson <chris@chris-wilson.co.uk>2010-08-04 08:55:32 -0400
committerEric Anholt <eric@anholt.net>2010-08-09 14:24:29 -0400
commit88f356b725c8a18c4da3ee0b6dcbc647418268f2 (patch)
treea87dc23ec8370579c3a8c341b52f22033501e49f
parente044218a8ecb560b6fad65912a4e7e509db40414 (diff)
drm/i915: Only emit flushes on active rings.
This avoids the excess flush and requests on idle rings (and spamming the debug log ;-) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c26
2 files changed, 19 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 906663b9929e..e7fb37995652 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -285,6 +285,9 @@ typedef struct drm_i915_private {
285 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 285 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
286 int vblank_pipe; 286 int vblank_pipe;
287 int num_pipe; 287 int num_pipe;
288 u32 flush_rings;
289#define FLUSH_RENDER_RING 0x1
290#define FLUSH_BSD_RING 0x2
288 291
289 /* For hangcheck timer */ 292 /* For hangcheck timer */
290#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ 293#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a4ed7ca8b4e..fc61542cce8a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3117,6 +3117,7 @@ static void
3117i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) 3117i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3118{ 3118{
3119 struct drm_device *dev = obj->dev; 3119 struct drm_device *dev = obj->dev;
3120 drm_i915_private_t *dev_priv = dev->dev_private;
3120 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 3121 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3121 uint32_t invalidate_domains = 0; 3122 uint32_t invalidate_domains = 0;
3122 uint32_t flush_domains = 0; 3123 uint32_t flush_domains = 0;
@@ -3179,6 +3180,13 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3179 obj->pending_write_domain = obj->write_domain; 3180 obj->pending_write_domain = obj->write_domain;
3180 obj->read_domains = obj->pending_read_domains; 3181 obj->read_domains = obj->pending_read_domains;
3181 3182
3183 if (flush_domains & I915_GEM_GPU_DOMAINS) {
3184 if (obj_priv->ring == &dev_priv->render_ring)
3185 dev_priv->flush_rings |= FLUSH_RENDER_RING;
3186 else if (obj_priv->ring == &dev_priv->bsd_ring)
3187 dev_priv->flush_rings |= FLUSH_BSD_RING;
3188 }
3189
3182 dev->invalidate_domains |= invalidate_domains; 3190 dev->invalidate_domains |= invalidate_domains;
3183 dev->flush_domains |= flush_domains; 3191 dev->flush_domains |= flush_domains;
3184#if WATCH_BUF 3192#if WATCH_BUF
@@ -3718,7 +3726,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3718 ring = &dev_priv->render_ring; 3726 ring = &dev_priv->render_ring;
3719 } 3727 }
3720 3728
3721
3722 if (args->buffer_count < 1) { 3729 if (args->buffer_count < 1) {
3723 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); 3730 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3724 return -EINVAL; 3731 return -EINVAL;
@@ -3892,6 +3899,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3892 */ 3899 */
3893 dev->invalidate_domains = 0; 3900 dev->invalidate_domains = 0;
3894 dev->flush_domains = 0; 3901 dev->flush_domains = 0;
3902 dev_priv->flush_rings = 0;
3895 3903
3896 for (i = 0; i < args->buffer_count; i++) { 3904 for (i = 0; i < args->buffer_count; i++) {
3897 struct drm_gem_object *obj = object_list[i]; 3905 struct drm_gem_object *obj = object_list[i];
@@ -3912,16 +3920,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3912 i915_gem_flush(dev, 3920 i915_gem_flush(dev,
3913 dev->invalidate_domains, 3921 dev->invalidate_domains,
3914 dev->flush_domains); 3922 dev->flush_domains);
3915 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) { 3923 if (dev_priv->flush_rings & FLUSH_RENDER_RING)
3916 (void)i915_add_request(dev, file_priv, 3924 (void)i915_add_request(dev, file_priv,
3917 dev->flush_domains, 3925 dev->flush_domains,
3918 &dev_priv->render_ring); 3926 &dev_priv->render_ring);
3919 3927 if (dev_priv->flush_rings & FLUSH_BSD_RING)
3920 if (HAS_BSD(dev)) 3928 (void)i915_add_request(dev, file_priv,
3921 (void)i915_add_request(dev, file_priv, 3929 dev->flush_domains,
3922 dev->flush_domains, 3930 &dev_priv->bsd_ring);
3923 &dev_priv->bsd_ring);
3924 }
3925 } 3931 }
3926 3932
3927 for (i = 0; i < args->buffer_count; i++) { 3933 for (i = 0; i < args->buffer_count; i++) {