PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver

This patch adds support for the APM X-Gene SoC 15Gbps Multi-purpose PHY.
This is the physical layer interface for the corresponding host
controller. Currently, only external clock and Gen3 SATA mode
are supported.

Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

3 files changed, 1758 insertions, 0 deletions

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2aead8b7dc60..8d3c49cc500f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -159,4 +159,11 @@ config PHY_EXYNOS5250_USB2
           particular SoC is compiled in the driver. In case of Exynos 5250 four
           phys are available - device, host, HSIC0 and HSIC.
 
+config PHY_XGENE
+        tristate "APM X-Gene 15Gbps PHY support"
+        depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
+        select GENERIC_PHY
+        help
+          This option enables support for APM X-Gene SoC multi-purpose PHY.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 8da05a841112..2faf78edc864 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-samsung-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4210_USB2)       += phy-exynos4210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4X12_USB2)       += phy-exynos4x12-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5250_USB2)       += phy-exynos5250-usb2.o
+obj-$(CONFIG_PHY_XGENE)                 += phy-xgene.o
diff --git a/drivers/phy/phy-xgene.c b/drivers/phy/phy-xgene.c
new file mode 100644
index 000000000000..4aa1ccd1511f
--- /dev/null
+++ b/drivers/phy/phy-xgene.c
@@ -0,0 +1,1750 @@
+/*
+ * AppliedMicro X-Gene Multi-purpose PHY driver
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Author: Loc Ho <lho@apm.com>
+ *         Tuan Phan <tphan@apm.com>
+ *         Suman Tripathi <stripathi@apm.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
+ * The first PLL clock macro is used for internal reference clock. The second
+ * PLL clock macro is used to generate the clock for the PHY. This driver
+ * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
+ * operate according to the mode of operation. The first PLL CMU is only
+ * required if internal clock is enabled.
+ *
+ * Logical Layer Out Of HW module units:
+ *
+ * -----------------
+ * | Internal      |    |------|
+ * | Ref PLL CMU   |----|      |     -------------    ---------
+ * ------------ ----    | MUX  |-----|PHY PLL CMU|----| Serdes|
+ *                      |      |     |           |    ---------
+ * External Clock ------|      |     -------------
+ *                      |------|
+ *
+ * The Ref PLL CMU CSR (Configuration System Registers) is accessed
+ * indirectly from the SDS offset at 0x2000. It is only required for
+ * internal reference clock.
+ * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
+ * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
+ *
+ * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
+ * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
+ * it is located outside the PHY IP. This is the case for the PHY located
+ * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
+ * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
+ *
+ * Currently, this driver only supports Gen3 SATA mode with external clock.
+ */
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/phy/phy.h>
+#include <linux/clk.h>
+
+/* Max 2 lanes per a PHY unit */
+#define MAX_LANE                        2
+
+/* Register offset inside the PHY */
+#define SERDES_PLL_INDIRECT_OFFSET      0x0000
+#define SERDES_PLL_REF_INDIRECT_OFFSET  0x2000
+#define SERDES_INDIRECT_OFFSET          0x0400
+#define SERDES_LANE_STRIDE              0x0200
+
+/* Some default Serdes parameters */
+#define DEFAULT_SATA_TXBOOST_GAIN       { 0x1e, 0x1e, 0x1e }
+#define DEFAULT_SATA_TXEYEDIRECTION     { 0x0, 0x0, 0x0 }
+#define DEFAULT_SATA_TXEYETUNING        { 0xa, 0xa, 0xa }
+#define DEFAULT_SATA_SPD_SEL            { 0x1, 0x3, 0x7 }
+#define DEFAULT_SATA_TXAMP              { 0x8, 0x8, 0x8 }
+#define DEFAULT_SATA_TXCN1              { 0x2, 0x2, 0x2 }
+#define DEFAULT_SATA_TXCN2              { 0x0, 0x0, 0x0 }
+#define DEFAULT_SATA_TXCP1              { 0xa, 0xa, 0xa }
+
+#define SATA_SPD_SEL_GEN3               0x7
+#define SATA_SPD_SEL_GEN2               0x3
+#define SATA_SPD_SEL_GEN1               0x1
+
+#define SSC_DISABLE                     0
+#define SSC_ENABLE                      1
+
+#define FBDIV_VAL_50M                   0x77
+#define REFDIV_VAL_50M                  0x1
+#define FBDIV_VAL_100M                  0x3B
+#define REFDIV_VAL_100M                 0x0
+
+/* SATA Clock/Reset CSR */
+#define SATACLKENREG                    0x00000000
+#define  SATA0_CORE_CLKEN               0x00000002
+#define  SATA1_CORE_CLKEN               0x00000004
+#define SATASRESETREG                   0x00000004
+#define  SATA_MEM_RESET_MASK            0x00000020
+#define  SATA_MEM_RESET_RD(src)         (((src) & 0x00000020) >> 5)
+#define  SATA_SDS_RESET_MASK            0x00000004
+#define  SATA_CSR_RESET_MASK            0x00000001
+#define  SATA_CORE_RESET_MASK           0x00000002
+#define  SATA_PMCLK_RESET_MASK          0x00000010
+#define  SATA_PCLK_RESET_MASK           0x00000008
+
+/* SDS CSR used for PHY Indirect access */
+#define SATA_ENET_SDS_PCS_CTL0          0x00000000
+#define  REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \
+                (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
+#define  REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \
+                (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
+#define SATA_ENET_SDS_CTL0              0x0000000c
+#define  REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \
+                (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
+#define SATA_ENET_SDS_CTL1              0x00000010
+#define  CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \
+                (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
+#define SATA_ENET_SDS_RST_CTL           0x00000024
+#define SATA_ENET_SDS_IND_CMD_REG       0x0000003c
+#define  CFG_IND_WR_CMD_MASK            0x00000001
+#define  CFG_IND_RD_CMD_MASK            0x00000002
+#define  CFG_IND_CMD_DONE_MASK          0x00000004
+#define  CFG_IND_ADDR_SET(dst, src) \
+                (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
+#define SATA_ENET_SDS_IND_RDATA_REG     0x00000040
+#define SATA_ENET_SDS_IND_WDATA_REG     0x00000044
+#define SATA_ENET_CLK_MACRO_REG         0x0000004c
+#define  I_RESET_B_SET(dst, src) \
+                (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
+#define  I_PLL_FBDIV_SET(dst, src) \
+                (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
+#define  I_CUSTOMEROV_SET(dst, src) \
+                (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
+#define  O_PLL_LOCK_RD(src)             (((src) & 0x40000000) >> 30)
+#define  O_PLL_READY_RD(src)            (((src) & 0x80000000) >> 31)
+
+/* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */
+#define CMU_REG0                        0x00000
+#define  CMU_REG0_PLL_REF_SEL_MASK      0x00002000
+#define  CMU_REG0_PLL_REF_SEL_SET(dst, src)     \
+                (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
+#define  CMU_REG0_PDOWN_MASK            0x00004000
+#define  CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \
+                (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
+#define CMU_REG1                        0x00002
+#define  CMU_REG1_PLL_CP_SET(dst, src) \
+                (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
+#define  CMU_REG1_PLL_MANUALCAL_SET(dst, src) \
+                (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
+#define  CMU_REG1_PLL_CP_SEL_SET(dst, src) \
+                (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
+#define  CMU_REG1_REFCLK_CMOS_SEL_MASK  0x00000001
+#define  CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \
+                (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
+#define CMU_REG2                        0x00004
+#define  CMU_REG2_PLL_REFDIV_SET(dst, src) \
+                (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
+#define  CMU_REG2_PLL_LFRES_SET(dst, src) \
+                (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
+#define  CMU_REG2_PLL_FBDIV_SET(dst, src) \
+                (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
+#define CMU_REG3                        0x00006
+#define  CMU_REG3_VCOVARSEL_SET(dst, src) \
+                (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))