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authorHiroshi Doyu <hdoyu@nvidia.com>2013-05-22 12:45:32 -0400
committerStephen Warren <swarren@nvidia.com>2013-05-28 18:13:50 -0400
commit885a8cfac681d8fc2005cf48622a6a1e3966974f (patch)
treeabf4a12e5a8a84171a4eea467732b32234192ffc
parent1a99ece9d0f8588b59a6142d518bd77e27c66932 (diff)
ARM: tegra20: convert device tree files to use CLK defines
Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra20-car.h moved for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi4
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts7
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts4
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi116
11 files changed, 94 insertions, 65 deletions
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 1321bce26c5c..2fcb3f2ca160 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -492,7 +492,9 @@
492 492
493 nvidia,ac97-controller = <&ac97>; 493 nvidia,ac97-controller = <&ac97>;
494 494
495 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 495 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
496 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
497 <&tegra_car TEGRA20_CLK_CDEV1>;
496 clock-names = "pll_a", "pll_a_out0", "mclk"; 498 clock-names = "pll_a", "pll_a_out0", "mclk";
497 }; 499 };
498 500
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 61d766f61187..d9f89cd879a7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -702,7 +702,9 @@
702 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) 702 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
703 GPIO_ACTIVE_HIGH>; 703 GPIO_ACTIVE_HIGH>;
704 704
705 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 705 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
706 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
707 <&tegra_car TEGRA20_CLK_CDEV1>;
706 clock-names = "pll_a", "pll_a_out0", "mclk"; 708 clock-names = "pll_a", "pll_a_out0", "mclk";
707 }; 709 };
708}; 710};
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 85d579234aeb..7580578903cf 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -59,7 +59,9 @@
59 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 59 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
60 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 60 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
61 61
62 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 62 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
63 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
64 <&tegra_car TEGRA20_CLK_CDEV1>;
63 clock-names = "pll_a", "pll_a_out0", "mclk"; 65 clock-names = "pll_a", "pll_a_out0", "mclk";
64 }; 66 };
65}; 67};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index d4b1d63fe909..cfd12763b1b2 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -277,7 +277,8 @@
277 clock-frequency = <80000>; 277 clock-frequency = <80000>;
278 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 278 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
279 slave-addr = <138>; 279 slave-addr = <138>;
280 clocks = <&tegra_car 67>, <&tegra_car 124>; 280 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
281 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
281 clock-names = "div-clk", "fast-clk"; 282 clock-names = "div-clk", "fast-clk";
282 }; 283 };
283 284
@@ -535,7 +536,9 @@
535 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 536 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
536 GPIO_ACTIVE_HIGH>; 537 GPIO_ACTIVE_HIGH>;
537 538
538 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 539 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
540 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
541 <&tegra_car TEGRA20_CLK_CDEV1>;
539 clock-names = "pll_a", "pll_a_out0", "mclk"; 542 clock-names = "pll_a", "pll_a_out0", "mclk";
540 }; 543 };
541}; 544};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 3374e16257dc..d7a358a6a647 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -53,7 +53,9 @@
53 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 53 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
54 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 54 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
55 55
56 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 56 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
57 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
58 <&tegra_car TEGRA20_CLK_CDEV1>;
57 clock-names = "pll_a", "pll_a_out0", "mclk"; 59 clock-names = "pll_a", "pll_a_out0", "mclk";
58 }; 60 };
59}; 61};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index ce6ceb5a4279..ab177b406b78 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -853,7 +853,9 @@
853 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 853 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
854 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; 854 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
855 855
856 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 856 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
857 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
858 <&tegra_car TEGRA20_CLK_CDEV1>;
857 clock-names = "pll_a", "pll_a_out0", "mclk"; 859 clock-names = "pll_a", "pll_a_out0", "mclk";
858 }; 860 };
859}; 861};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9eaa9621a17c..c572c43751b1 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -54,7 +54,9 @@
54 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 54 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
55 GPIO_ACTIVE_HIGH>; 55 GPIO_ACTIVE_HIGH>;
56 56
57 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 57 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
59 <&tegra_car TEGRA20_CLK_CDEV1>;
58 clock-names = "pll_a", "pll_a_out0", "mclk"; 60 clock-names = "pll_a", "pll_a_out0", "mclk";
59 }; 61 };
60}; 62};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 4257ab44fe84..170159910455 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -419,7 +419,9 @@
419 nvidia,i2s-controller = <&tegra_i2s1>; 419 nvidia,i2s-controller = <&tegra_i2s1>;
420 nvidia,audio-codec = <&codec>; 420 nvidia,audio-codec = <&codec>;
421 421
422 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 422 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
423 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
424 <&tegra_car TEGRA20_CLK_CDEV1>;
423 clock-names = "pll_a", "pll_a_out0", "mclk"; 425 clock-names = "pll_a", "pll_a_out0", "mclk";
424 }; 426 };
425}; 427};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index e0c0cc15d2b4..7f8c28d1121f 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -654,7 +654,9 @@
654 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) 654 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
655 GPIO_ACTIVE_HIGH>; 655 GPIO_ACTIVE_HIGH>;
656 656
657 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 657 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
658 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
659 <&tegra_car TEGRA20_CLK_CDEV1>;
658 clock-names = "pll_a", "pll_a_out0", "mclk"; 660 clock-names = "pll_a", "pll_a_out0", "mclk";
659 }; 661 };
660}; 662};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 2b921204395a..ea078ab8edeb 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -613,7 +613,9 @@
613 nvidia,i2s-controller = <&tegra_i2s1>; 613 nvidia,i2s-controller = <&tegra_i2s1>;
614 nvidia,audio-codec = <&codec>; 614 nvidia,audio-codec = <&codec>;
615 615
616 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 616 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
617 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
618 <&tegra_car TEGRA20_CLK_CDEV1>;
617 clock-names = "pll_a", "pll_a_out0", "mclk"; 619 clock-names = "pll_a", "pll_a_out0", "mclk";
618 }; 620 };
619}; 621};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f9c6ecad043b..9653fd8288d2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,3 +1,4 @@
1#include <dt-bindings/clock/tegra20-car.h>
1#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3 4
@@ -20,7 +21,7 @@
20 reg = <0x50000000 0x00024000>; 21 reg = <0x50000000 0x00024000>;
21 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
22 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
23 clocks = <&tegra_car 28>; 24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
24 25
25 #address-cells = <1>; 26 #address-cells = <1>;
26 #size-cells = <1>; 27 #size-cells = <1>;
@@ -31,48 +32,49 @@
31 compatible = "nvidia,tegra20-mpe"; 32 compatible = "nvidia,tegra20-mpe";
32 reg = <0x54040000 0x00040000>; 33 reg = <0x54040000 0x00040000>;
33 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&tegra_car 60>; 35 clocks = <&tegra_car TEGRA20_CLK_MPE>;
35 }; 36 };
36 37
37 vi { 38 vi {
38 compatible = "nvidia,tegra20-vi"; 39 compatible = "nvidia,tegra20-vi";
39 reg = <0x54080000 0x00040000>; 40 reg = <0x54080000 0x00040000>;
40 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
41 clocks = <&tegra_car 100>; 42 clocks = <&tegra_car TEGRA20_CLK_VI>;
42 }; 43 };
43 44
44 epp { 45 epp {
45 compatible = "nvidia,tegra20-epp"; 46 compatible = "nvidia,tegra20-epp";
46 reg = <0x540c0000 0x00040000>; 47 reg = <0x540c0000 0x00040000>;
47 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&tegra_car 19>; 49 clocks = <&tegra_car TEGRA20_CLK_EPP>;
49 }; 50 };
50 51
51 isp { 52 isp {
52 compatible = "nvidia,tegra20-isp"; 53 compatible = "nvidia,tegra20-isp";
53 reg = <0x54100000 0x00040000>; 54 reg = <0x54100000 0x00040000>;
54 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&tegra_car 23>; 56 clocks = <&tegra_car TEGRA20_CLK_ISP>;
56 }; 57 };
57 58
58 gr2d { 59 gr2d {
59 compatible = "nvidia,tegra20-gr2d"; 60 compatible = "nvidia,tegra20-gr2d";
60 reg = <0x54140000 0x00040000>; 61 reg = <0x54140000 0x00040000>;
61 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
62 clocks = <&tegra_car 21>; 63 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
63 }; 64 };
64 65
65 gr3d { 66 gr3d {
66 compatible = "nvidia,tegra20-gr3d"; 67 compatible = "nvidia,tegra20-gr3d";
67 reg = <0x54180000 0x00040000>; 68 reg = <0x54180000 0x00040000>;
68 clocks = <&tegra_car 24>; 69 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
69 }; 70 };
70 71
71 dc@54200000 { 72 dc@54200000 {
72 compatible = "nvidia,tegra20-dc"; 73 compatible = "nvidia,tegra20-dc";
73 reg = <0x54200000 0x00040000>; 74 reg = <0x54200000 0x00040000>;
74 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
75 clocks = <&tegra_car 27>, <&tegra_car 121>; 76 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
77 <&tegra_car TEGRA20_CLK_PLL_P>;
76 clock-names = "disp1", "parent"; 78 clock-names = "disp1", "parent";
77 79
78 rgb { 80 rgb {
@@ -84,7 +86,8 @@
84 compatible = "nvidia,tegra20-dc"; 86 compatible = "nvidia,tegra20-dc";
85 reg = <0x54240000 0x00040000>; 87 reg = <0x54240000 0x00040000>;
86 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 88 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
87 clocks = <&tegra_car 26>, <&tegra_car 121>; 89 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
90 <&tegra_car TEGRA20_CLK_PLL_P>;
88 clock-names = "disp2", "parent"; 91 clock-names = "disp2", "parent";
89 92
90 rgb { 93 rgb {
@@ -96,7 +99,8 @@
96 compatible = "nvidia,tegra20-hdmi"; 99 compatible = "nvidia,tegra20-hdmi";
97 reg = <0x54280000 0x00040000>; 100 reg = <0x54280000 0x00040000>;
98 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 101 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&tegra_car 51>, <&tegra_car 117>; 102 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
103 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
100 clock-names = "hdmi", "parent"; 104 clock-names = "hdmi", "parent";
101 status = "disabled"; 105 status = "disabled";
102 }; 106 };
@@ -105,14 +109,14 @@
105 compatible = "nvidia,tegra20-tvo"; 109 compatible = "nvidia,tegra20-tvo";
106 reg = <0x542c0000 0x00040000>; 110 reg = <0x542c0000 0x00040000>;
107 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&tegra_car 102>; 112 clocks = <&tegra_car TEGRA20_CLK_TVO>;
109 status = "disabled"; 113 status = "disabled";
110 }; 114 };
111 115
112 dsi { 116 dsi {
113 compatible = "nvidia,tegra20-dsi"; 117 compatible = "nvidia,tegra20-dsi";
114 reg = <0x54300000 0x00040000>; 118 reg = <0x54300000 0x00040000>;
115 clocks = <&tegra_car 48>; 119 clocks = <&tegra_car TEGRA20_CLK_DSI>;
116 status = "disabled"; 120 status = "disabled";
117 }; 121 };
118 }; 122 };
@@ -122,7 +126,7 @@
122 reg = <0x50040600 0x20>; 126 reg = <0x50040600 0x20>;
123 interrupts = <GIC_PPI 13 127 interrupts = <GIC_PPI 13
124 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 128 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
125 clocks = <&tegra_car 132>; 129 clocks = <&tegra_car TEGRA20_CLK_TWD>;
126 }; 130 };
127 131
128 intc: interrupt-controller { 132 intc: interrupt-controller {
@@ -149,7 +153,7 @@
149 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 155 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&tegra_car 5>; 156 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
153 }; 157 };
154 158
155 tegra_car: clock { 159 tegra_car: clock {
@@ -177,7 +181,7 @@
177 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&tegra_car 34>; 184 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
181 }; 185 };
182 186
183 ahb { 187 ahb {
@@ -219,7 +223,7 @@
219 reg = <0x70002000 0x200>; 223 reg = <0x70002000 0x200>;
220 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 224 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
221 nvidia,dma-request-selector = <&apbdma 12>; 225 nvidia,dma-request-selector = <&apbdma 12>;
222 clocks = <&tegra_car 3>; 226 clocks = <&tegra_car TEGRA20_CLK_AC97>;
223 status = "disabled"; 227 status = "disabled";
224 }; 228 };
225 229
@@ -228,7 +232,7 @@
228 reg = <0x70002800 0x200>; 232 reg = <0x70002800 0x200>;
229 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
230 nvidia,dma-request-selector = <&apbdma 2>; 234 nvidia,dma-request-selector = <&apbdma 2>;
231 clocks = <&tegra_car 11>; 235 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
232 status = "disabled"; 236 status = "disabled";
233 }; 237 };
234 238
@@ -237,7 +241,7 @@
237 reg = <0x70002a00 0x200>; 241 reg = <0x70002a00 0x200>;
238 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 242 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
239 nvidia,dma-request-selector = <&apbdma 1>; 243 nvidia,dma-request-selector = <&apbdma 1>;
240 clocks = <&tegra_car 18>; 244 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
241 status = "disabled"; 245 status = "disabled";
242 }; 246 };
243 247
@@ -254,7 +258,7 @@
254 reg-shift = <2>; 258 reg-shift = <2>;
255 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
256 nvidia,dma-request-selector = <&apbdma 8>; 260 nvidia,dma-request-selector = <&apbdma 8>;
257 clocks = <&tegra_car 6>; 261 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
258 status = "disabled"; 262 status = "disabled";
259 }; 263 };
260 264
@@ -264,7 +268,7 @@
264 reg-shift = <2>; 268 reg-shift = <2>;
265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
266 nvidia,dma-request-selector = <&apbdma 9>; 270 nvidia,dma-request-selector = <&apbdma 9>;
267 clocks = <&tegra_car 96>; 271 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
268 status = "disabled"; 272 status = "disabled";
269 }; 273 };
270 274
@@ -274,7 +278,7 @@
274 reg-shift = <2>; 278 reg-shift = <2>;
275 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 279 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
276 nvidia,dma-request-selector = <&apbdma 10>; 280 nvidia,dma-request-selector = <&apbdma 10>;
277 clocks = <&tegra_car 55>; 281 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
278 status = "disabled"; 282 status = "disabled";
279 }; 283 };
280 284
@@ -284,7 +288,7 @@
284 reg-shift = <2>; 288 reg-shift = <2>;
285 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 289 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
286 nvidia,dma-request-selector = <&apbdma 19>; 290 nvidia,dma-request-selector = <&apbdma 19>;
287 clocks = <&tegra_car 65>; 291 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
288 status = "disabled"; 292 status = "disabled";
289 }; 293 };
290 294
@@ -294,7 +298,7 @@
294 reg-shift = <2>; 298 reg-shift = <2>;
295 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 299 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
296 nvidia,dma-request-selector = <&apbdma 20>; 300 nvidia,dma-request-selector = <&apbdma 20>;
297 clocks = <&tegra_car 66>; 301 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
298 status = "disabled"; 302 status = "disabled";
299 }; 303 };
300 304
@@ -302,7 +306,7 @@
302 compatible = "nvidia,tegra20-pwm"; 306 compatible = "nvidia,tegra20-pwm";
303 reg = <0x7000a000 0x100>; 307 reg = <0x7000a000 0x100>;
304 #pwm-cells = <2>; 308 #pwm-cells = <2>;
305 clocks = <&tegra_car 17>; 309 clocks = <&tegra_car TEGRA20_CLK_PWM>;
306 status = "disabled"; 310 status = "disabled";
307 }; 311 };
308 312
@@ -310,7 +314,7 @@
310 compatible = "nvidia,tegra20-rtc"; 314 compatible = "nvidia,tegra20-rtc";
311 reg = <0x7000e000 0x100>; 315 reg = <0x7000e000 0x100>;
312 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 316 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&tegra_car 4>; 317 clocks = <&tegra_car TEGRA20_CLK_RTC>;
314 }; 318 };
315 319
316 i2c@7000c000 { 320 i2c@7000c000 {
@@ -319,7 +323,8 @@
319 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 323 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>; 324 #address-cells = <1>;
321 #size-cells = <0>; 325 #size-cells = <0>;
322 clocks = <&tegra_car 12>, <&tegra_car 124>; 326 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
327 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
323 clock-names = "div-clk", "fast-clk"; 328 clock-names = "div-clk", "fast-clk";
324 status = "disabled"; 329 status = "disabled";
325 }; 330 };
@@ -331,7 +336,7 @@
331 nvidia,dma-request-selector = <&apbdma 11>; 336 nvidia,dma-request-selector = <&apbdma 11>;
332 #address-cells = <1>; 337 #address-cells = <1>;
333 #size-cells = <0>; 338 #size-cells = <0>;
334 clocks = <&tegra_car 43>; 339 clocks = <&tegra_car TEGRA20_CLK_SPI>;
335 status = "disabled"; 340 status = "disabled";
336 }; 341 };
337 342
@@ -341,7 +346,8 @@
341 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 346 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>; 347 #address-cells = <1>;
343 #size-cells = <0>; 348 #size-cells = <0>;
344 clocks = <&tegra_car 54>, <&tegra_car 124>; 349 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
350 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
345 clock-names = "div-clk", "fast-clk"; 351 clock-names = "div-clk", "fast-clk";
346 status = "disabled"; 352 status = "disabled";
347 }; 353 };
@@ -352,7 +358,8 @@
352 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>; 359 #address-cells = <1>;
354 #size-cells = <0>; 360 #size-cells = <0>;
355 clocks = <&tegra_car 67>, <&tegra_car 124>; 361 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
362 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
356 clock-names = "div-clk", "fast-clk"; 363 clock-names = "div-clk", "fast-clk";
357 status = "disabled"; 364 status = "disabled";
358 }; 365 };
@@ -363,7 +370,8 @@
363 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 370 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>; 371 #address-cells = <1>;
365 #size-cells = <0>; 372 #size-cells = <0>;
366 clocks = <&tegra_car 47>, <&tegra_car 124>; 373 clocks = <&tegra_car TEGRA20_CLK_DVC>,
374 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
367 clock-names = "div-clk", "fast-clk"; 375 clock-names = "div-clk", "fast-clk";
368 status = "disabled"; 376 status = "disabled";
369 }; 377 };
@@ -375,7 +383,7 @@
375 nvidia,dma-request-selector = <&apbdma 15>; 383 nvidia,dma-request-selector = <&apbdma 15>;
376 #address-cells = <1>; 384 #address-cells = <1>;
377 #size-cells = <0>; 385 #size-cells = <0>;
378 clocks = <&tegra_car 41>; 386 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
379 status = "disabled"; 387 status = "disabled";
380 }; 388 };
381 389
@@ -386,7 +394,7 @@
386 nvidia,dma-request-selector = <&apbdma 16>; 394 nvidia,dma-request-selector = <&apbdma 16>;
387 #address-cells = <1>; 395 #address-cells = <1>;
388 #size-cells = <0>; 396 #size-cells = <0>;
389 clocks = <&tegra_car 44>; 397 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
390 status = "disabled"; 398 status = "disabled";
391 }; 399 };
392 400
@@ -397,7 +405,7 @@
397 nvidia,dma-request-selector = <&apbdma 17>; 405 nvidia,dma-request-selector = <&apbdma 17>;
398 #address-cells = <1>; 406 #address-cells = <1>;
399 #size-cells = <0>; 407 #size-cells = <0>;
400 clocks = <&tegra_car 46>; 408 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
401 status = "disabled"; 409 status = "disabled";
402 }; 410 };
403 411
@@ -408,7 +416,7 @@
408 nvidia,dma-request-selector = <&apbdma 18>; 416 nvidia,dma-request-selector = <&apbdma 18>;
409 #address-cells = <1>; 417 #address-cells = <1>;
410 #size-cells = <0>; 418 #size-cells = <0>;
411 clocks = <&tegra_car 68>; 419 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
412 status = "disabled"; 420 status = "disabled";
413 }; 421 };
414 422
@@ -416,14 +424,14 @@
416 compatible = "nvidia,tegra20-kbc"; 424 compatible = "nvidia,tegra20-kbc";
417 reg = <0x7000e200 0x100>; 425 reg = <0x7000e200 0x100>;
418 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 426 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&tegra_car 36>; 427 clocks = <&tegra_car TEGRA20_CLK_KBC>;
420 status = "disabled"; 428 status = "disabled";
421 }; 429 };
422 430
423 pmc { 431 pmc {
424 compatible = "nvidia,tegra20-pmc"; 432 compatible = "nvidia,tegra20-pmc";
425 reg = <0x7000e400 0x400>; 433 reg = <0x7000e400 0x400>;
426 clocks = <&tegra_car 110>, <&clk32k_in>; 434 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
427 clock-names = "pclk", "clk32k_in"; 435 clock-names = "pclk", "clk32k_in";
428 }; 436 };
429 437
@@ -453,7 +461,7 @@
453 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 461 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
454 phy_type = "utmi"; 462 phy_type = "utmi";
455 nvidia,has-legacy-mode; 463 nvidia,has-legacy-mode;
456 clocks = <&tegra_car 22>; 464 clocks = <&tegra_car TEGRA20_CLK_USBD>;
457 nvidia,needs-double-reset; 465 nvidia,needs-double-reset;
458 nvidia,phy = <&phy1>; 466 nvidia,phy = <&phy1>;
459 status = "disabled"; 467 status = "disabled";
@@ -463,10 +471,10 @@
463 compatible = "nvidia,tegra20-usb-phy"; 471 compatible = "nvidia,tegra20-usb-phy";
464 reg = <0xc5000000 0x4000 0xc5000000 0x4000>; 472 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
465 phy_type = "utmi"; 473 phy_type = "utmi";
466 clocks = <&tegra_car 22>, 474 clocks = <&tegra_car TEGRA20_CLK_USBD>,
467 <&tegra_car 127>, 475 <&tegra_car TEGRA20_CLK_PLL_U>,
468 <&tegra_car 106>, 476 <&tegra_car TEGRA20_CLK_CLK_M>,
469 <&tegra_car 22>; 477 <&tegra_car TEGRA20_CLK_USBD>;
470 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 478 clock-names = "reg", "pll_u", "timer", "utmi-pads";
471 nvidia,has-legacy-mode; 479 nvidia,has-legacy-mode;
472 hssync_start_delay = <9>; 480 hssync_start_delay = <9>;
@@ -484,7 +492,7 @@
484 reg = <0xc5004000 0x4000>; 492 reg = <0xc5004000 0x4000>;
485 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 493 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
486 phy_type = "ulpi"; 494 phy_type = "ulpi";
487 clocks = <&tegra_car 58>; 495 clocks = <&tegra_car TEGRA20_CLK_USB2>;
488 nvidia,phy = <&phy2>; 496 nvidia,phy = <&phy2>;
489 status = "disabled"; 497 status = "disabled";
490 }; 498 };
@@ -493,9 +501,9 @@
493 compatible = "nvidia,tegra20-usb-phy"; 501 compatible = "nvidia,tegra20-usb-phy";
494 reg = <0xc5004000 0x4000>; 502 reg = <0xc5004000 0x4000>;
495 phy_type = "ulpi"; 503 phy_type = "ulpi";
496 clocks = <&tegra_car 58>, 504 clocks = <&tegra_car TEGRA20_CLK_USB2>,
497 <&tegra_car 127>, 505 <&tegra_car TEGRA20_CLK_PLL_U>,
498 <&tegra_car 93>; 506 <&tegra_car TEGRA20_CLK_CDEV2>;
499 clock-names = "reg", "pll_u", "ulpi-link"; 507 clock-names = "reg", "pll_u", "ulpi-link";
500 status = "disabled"; 508 status = "disabled";
501 }; 509 };
@@ -505,7 +513,7 @@
505 reg = <0xc5008000 0x4000>; 513 reg = <0xc5008000 0x4000>;
506 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 514 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
507 phy_type = "utmi"; 515 phy_type = "utmi";
508 clocks = <&tegra_car 59>; 516 clocks = <&tegra_car TEGRA20_CLK_USB3>;
509 nvidia,phy = <&phy3>; 517 nvidia,phy = <&phy3>;
510 status = "disabled"; 518 status = "disabled";
511 }; 519 };
@@ -514,10 +522,10 @@
514 compatible = "nvidia,tegra20-usb-phy"; 522 compatible = "nvidia,tegra20-usb-phy";
515 reg = <0xc5008000 0x4000 0xc5000000 0x4000>; 523 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
516 phy_type = "utmi"; 524 phy_type = "utmi";
517 clocks = <&tegra_car 59>, 525 clocks = <&tegra_car TEGRA20_CLK_USB3>,
518 <&tegra_car 127>, 526 <&tegra_car TEGRA20_CLK_PLL_U>,
519 <&tegra_car 106>, 527 <&tegra_car TEGRA20_CLK_CLK_M>,
520 <&tegra_car 22>; 528 <&tegra_car TEGRA20_CLK_USBD>;
521 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 529 clock-names = "reg", "pll_u", "timer", "utmi-pads";
522 hssync_start_delay = <9>; 530 hssync_start_delay = <9>;
523 idle_wait_delay = <17>; 531 idle_wait_delay = <17>;
@@ -533,7 +541,7 @@
533 compatible = "nvidia,tegra20-sdhci"; 541 compatible = "nvidia,tegra20-sdhci";
534 reg = <0xc8000000 0x200>; 542 reg = <0xc8000000 0x200>;
535 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 543 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&tegra_car 14>; 544 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
537 status = "disabled"; 545 status = "disabled";
538 }; 546 };
539 547
@@ -541,7 +549,7 @@
541 compatible = "nvidia,tegra20-sdhci"; 549 compatible = "nvidia,tegra20-sdhci";
542 reg = <0xc8000200 0x200>; 550 reg = <0xc8000200 0x200>;
543 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 551 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&tegra_car 9>; 552 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
545 status = "disabled"; 553 status = "disabled";
546 }; 554 };
547 555
@@ -549,7 +557,7 @@
549 compatible = "nvidia,tegra20-sdhci"; 557 compatible = "nvidia,tegra20-sdhci";
550 reg = <0xc8000400 0x200>; 558 reg = <0xc8000400 0x200>;
551 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 559 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&tegra_car 69>; 560 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
553 status = "disabled"; 561 status = "disabled";
554 }; 562 };
555 563
@@ -557,7 +565,7 @@
557 compatible = "nvidia,tegra20-sdhci"; 565 compatible = "nvidia,tegra20-sdhci";
558 reg = <0xc8000600 0x200>; 566 reg = <0xc8000600 0x200>;
559 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 567 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&tegra_car 15>; 568 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
561 status = "disabled"; 569 status = "disabled";
562 }; 570 };
563 571
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 16:26:27 -0400