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authorStephen Warren <swarren@nvidia.com>2014-02-18 18:51:58 -0500
committerOlof Johansson <olof@lixom.net>2014-02-18 23:30:59 -0500
commit8859685785bfafadf9bc922dd3a2278e59886947 (patch)
treecf73871e0e0ccb40547685edf64d0e7a43c81274
parent688b56b485578465f6619b9529d08c2b95641915 (diff)
ARM: tegra: only run PL310 init on systems with one
Fix tegra_init_cache() to check whether the system has a PL310 cache before touching the PL310 registers. This prevents access to non-existent registers on Tegra114 and later. Note for stable kernels: In <= v3.12, the file to patch is arch/arm/mach-tegra/common.c. Cc: <stable@vger.kernel.org> # v3.9+ Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/mach-tegra/tegra.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 303a285d80fd..6191603379e1 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -73,10 +73,20 @@ u32 tegra_uart_config[3] = {
73static void __init tegra_init_cache(void) 73static void __init tegra_init_cache(void)
74{ 74{
75#ifdef CONFIG_CACHE_L2X0 75#ifdef CONFIG_CACHE_L2X0
76 static const struct of_device_id pl310_ids[] __initconst = {
77 { .compatible = "arm,pl310-cache", },
78 {}
79 };
80
81 struct device_node *np;
76 int ret; 82 int ret;
77 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; 83 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
78 u32 aux_ctrl, cache_type; 84 u32 aux_ctrl, cache_type;
79 85
86 np = of_find_matching_node(NULL, pl310_ids);
87 if (!np)
88 return;
89
80 cache_type = readl(p + L2X0_CACHE_TYPE); 90 cache_type = readl(p + L2X0_CACHE_TYPE);
81 aux_ctrl = (cache_type & 0x700) << (17-8); 91 aux_ctrl = (cache_type & 0x700) << (17-8);
82 aux_ctrl |= 0x7C400001; 92 aux_ctrl |= 0x7C400001;