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authorShannon Nelson <shannon.nelson@intel.com>2014-06-04 16:41:17 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2014-07-01 02:45:44 -0400
commit87dc346433edbc069bf547402d321c1f419b2dcc (patch)
tree78d70b1ad0730354558e8833a7de5778104ccc77
parent4135ab8208048a1586385fae1298726d7dacfc26 (diff)
i40e/i40evf: Add base address registers to aq struct
Add the Base Address High and Low to the admin queue struct to simplify another bit of "which context" logic in the config routines. Change-ID: Iae195a7da3baffc1a9d522119e1e2b427068ad07 Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_adminq.c58
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_adminq.h2
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40e_adminq.c58
-rw-r--r--drivers/net/ethernet/intel/i40evf/i40e_adminq.h2
4 files changed, 44 insertions, 76 deletions
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
index 95aab708a88d..87f1d8bcb095 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
@@ -55,16 +55,24 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
55 hw->aq.asq.tail = I40E_VF_ATQT1; 55 hw->aq.asq.tail = I40E_VF_ATQT1;
56 hw->aq.asq.head = I40E_VF_ATQH1; 56 hw->aq.asq.head = I40E_VF_ATQH1;
57 hw->aq.asq.len = I40E_VF_ATQLEN1; 57 hw->aq.asq.len = I40E_VF_ATQLEN1;
58 hw->aq.asq.bal = I40E_VF_ATQBAL1;
59 hw->aq.asq.bah = I40E_VF_ATQBAH1;
58 hw->aq.arq.tail = I40E_VF_ARQT1; 60 hw->aq.arq.tail = I40E_VF_ARQT1;
59 hw->aq.arq.head = I40E_VF_ARQH1; 61 hw->aq.arq.head = I40E_VF_ARQH1;
60 hw->aq.arq.len = I40E_VF_ARQLEN1; 62 hw->aq.arq.len = I40E_VF_ARQLEN1;
63 hw->aq.arq.bal = I40E_VF_ARQBAL1;
64 hw->aq.arq.bah = I40E_VF_ARQBAH1;
61 } else { 65 } else {
62 hw->aq.asq.tail = I40E_PF_ATQT; 66 hw->aq.asq.tail = I40E_PF_ATQT;
63 hw->aq.asq.head = I40E_PF_ATQH; 67 hw->aq.asq.head = I40E_PF_ATQH;
64 hw->aq.asq.len = I40E_PF_ATQLEN; 68 hw->aq.asq.len = I40E_PF_ATQLEN;
69 hw->aq.asq.bal = I40E_PF_ATQBAL;
70 hw->aq.asq.bah = I40E_PF_ATQBAH;
65 hw->aq.arq.tail = I40E_PF_ARQT; 71 hw->aq.arq.tail = I40E_PF_ARQT;
66 hw->aq.arq.head = I40E_PF_ARQH; 72 hw->aq.arq.head = I40E_PF_ARQH;
67 hw->aq.arq.len = I40E_PF_ARQLEN; 73 hw->aq.arq.len = I40E_PF_ARQLEN;
74 hw->aq.arq.bal = I40E_PF_ARQBAL;
75 hw->aq.arq.bah = I40E_PF_ARQBAH;
68 } 76 }
69} 77}
70 78
@@ -300,27 +308,14 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
300 wr32(hw, hw->aq.asq.head, 0); 308 wr32(hw, hw->aq.asq.head, 0);
301 wr32(hw, hw->aq.asq.tail, 0); 309 wr32(hw, hw->aq.asq.tail, 0);
302 310
303 if (hw->mac.type == I40E_MAC_VF) { 311 /* set starting point */
304 /* configure the transmit queue */ 312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
305 wr32(hw, I40E_VF_ATQBAH1, 313 I40E_PF_ATQLEN_ATQENABLE_MASK));
306 upper_32_bits(hw->aq.asq.desc_buf.pa)); 314 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
307 wr32(hw, I40E_VF_ATQBAL1, 315 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
308 lower_32_bits(hw->aq.asq.desc_buf.pa));
309 wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
310 I40E_VF_ATQLEN1_ATQENABLE_MASK));
311 reg = rd32(hw, I40E_VF_ATQBAL1);
312 } else {
313 /* configure the transmit queue */
314 wr32(hw, I40E_PF_ATQBAH,
315 upper_32_bits(hw->aq.asq.desc_buf.pa));
316 wr32(hw, I40E_PF_ATQBAL,
317 lower_32_bits(hw->aq.asq.desc_buf.pa));
318 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
319 I40E_PF_ATQLEN_ATQENABLE_MASK));
320 reg = rd32(hw, I40E_PF_ATQBAL);
321 }
322 316
323 /* Check one register to verify that config was applied */ 317 /* Check one register to verify that config was applied */
318 reg = rd32(hw, hw->aq.asq.bal);
324 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) 319 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
325 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 320 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
326 321
@@ -342,30 +337,17 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
342 wr32(hw, hw->aq.arq.head, 0); 337 wr32(hw, hw->aq.arq.head, 0);
343 wr32(hw, hw->aq.arq.tail, 0); 338 wr32(hw, hw->aq.arq.tail, 0);
344 339
345 if (hw->mac.type == I40E_MAC_VF) { 340 /* set starting point */
346 /* configure the receive queue */ 341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
347 wr32(hw, I40E_VF_ARQBAH1, 342 I40E_PF_ARQLEN_ARQENABLE_MASK));
348 upper_32_bits(hw->aq.arq.desc_buf.pa)); 343 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
349 wr32(hw, I40E_VF_ARQBAL1, 344 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
350 lower_32_bits(hw->aq.arq.desc_buf.pa));
351 wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
352 I40E_VF_ARQLEN1_ARQENABLE_MASK));
353 reg = rd32(hw, I40E_VF_ARQBAL1);
354 } else {
355 /* configure the receive queue */
356 wr32(hw, I40E_PF_ARQBAH,
357 upper_32_bits(hw->aq.arq.desc_buf.pa));
358 wr32(hw, I40E_PF_ARQBAL,
359 lower_32_bits(hw->aq.arq.desc_buf.pa));
360 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
361 I40E_PF_ARQLEN_ARQENABLE_MASK));
362 reg = rd32(hw, I40E_PF_ARQBAL);
363 }
364 345
365 /* Update tail in the HW to post pre-allocated buffers */ 346 /* Update tail in the HW to post pre-allocated buffers */
366 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); 347 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
367 348
368 /* Check one register to verify that config was applied */ 349 /* Check one register to verify that config was applied */
350 reg = rd32(hw, hw->aq.arq.bal);
369 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) 351 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
370 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 352 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
371 353
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.h b/drivers/net/ethernet/intel/i40e/i40e_adminq.h
index b1552fbc48a0..c6142ba3a10d 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_adminq.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.h
@@ -56,6 +56,8 @@ struct i40e_adminq_ring {
56 u32 head; 56 u32 head;
57 u32 tail; 57 u32 tail;
58 u32 len; 58 u32 len;
59 u32 bah;
60 u32 bal;
59}; 61};
60 62
61/* ASQ transaction details */ 63/* ASQ transaction details */
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
index 15853fd699a4..79a30dd8c26f 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
@@ -53,16 +53,24 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
53 hw->aq.asq.tail = I40E_VF_ATQT1; 53 hw->aq.asq.tail = I40E_VF_ATQT1;
54 hw->aq.asq.head = I40E_VF_ATQH1; 54 hw->aq.asq.head = I40E_VF_ATQH1;
55 hw->aq.asq.len = I40E_VF_ATQLEN1; 55 hw->aq.asq.len = I40E_VF_ATQLEN1;
56 hw->aq.asq.bal = I40E_VF_ATQBAL1;
57 hw->aq.asq.bah = I40E_VF_ATQBAH1;
56 hw->aq.arq.tail = I40E_VF_ARQT1; 58 hw->aq.arq.tail = I40E_VF_ARQT1;
57 hw->aq.arq.head = I40E_VF_ARQH1; 59 hw->aq.arq.head = I40E_VF_ARQH1;
58 hw->aq.arq.len = I40E_VF_ARQLEN1; 60 hw->aq.arq.len = I40E_VF_ARQLEN1;
61 hw->aq.arq.bal = I40E_VF_ARQBAL1;
62 hw->aq.arq.bah = I40E_VF_ARQBAH1;
59 } else { 63 } else {
60 hw->aq.asq.tail = I40E_PF_ATQT; 64 hw->aq.asq.tail = I40E_PF_ATQT;
61 hw->aq.asq.head = I40E_PF_ATQH; 65 hw->aq.asq.head = I40E_PF_ATQH;
62 hw->aq.asq.len = I40E_PF_ATQLEN; 66 hw->aq.asq.len = I40E_PF_ATQLEN;
67 hw->aq.asq.bal = I40E_PF_ATQBAL;
68 hw->aq.asq.bah = I40E_PF_ATQBAH;
63 hw->aq.arq.tail = I40E_PF_ARQT; 69 hw->aq.arq.tail = I40E_PF_ARQT;
64 hw->aq.arq.head = I40E_PF_ARQH; 70 hw->aq.arq.head = I40E_PF_ARQH;
65 hw->aq.arq.len = I40E_PF_ARQLEN; 71 hw->aq.arq.len = I40E_PF_ARQLEN;
72 hw->aq.arq.bal = I40E_PF_ARQBAL;
73 hw->aq.arq.bah = I40E_PF_ARQBAH;
66 } 74 }
67} 75}
68 76
@@ -298,27 +306,14 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
298 wr32(hw, hw->aq.asq.head, 0); 306 wr32(hw, hw->aq.asq.head, 0);
299 wr32(hw, hw->aq.asq.tail, 0); 307 wr32(hw, hw->aq.asq.tail, 0);
300 308
301 if (hw->mac.type == I40E_MAC_VF) { 309 /* set starting point */
302 /* configure the transmit queue */ 310 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
303 wr32(hw, I40E_VF_ATQBAH1, 311 I40E_PF_ATQLEN_ATQENABLE_MASK));
304 upper_32_bits(hw->aq.asq.desc_buf.pa)); 312 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
305 wr32(hw, I40E_VF_ATQBAL1, 313 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
306 lower_32_bits(hw->aq.asq.desc_buf.pa));
307 wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
308 I40E_VF_ATQLEN1_ATQENABLE_MASK));
309 reg = rd32(hw, I40E_VF_ATQBAL1);
310 } else {
311 /* configure the transmit queue */
312 wr32(hw, I40E_PF_ATQBAH,
313 upper_32_bits(hw->aq.asq.desc_buf.pa));
314 wr32(hw, I40E_PF_ATQBAL,
315 lower_32_bits(hw->aq.asq.desc_buf.pa));
316 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
317 I40E_PF_ATQLEN_ATQENABLE_MASK));
318 reg = rd32(hw, I40E_PF_ATQBAL);
319 }
320 314
321 /* Check one register to verify that config was applied */ 315 /* Check one register to verify that config was applied */
316 reg = rd32(hw, hw->aq.asq.bal);
322 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) 317 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
323 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 318 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
324 319
@@ -340,30 +335,17 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
340 wr32(hw, hw->aq.arq.head, 0); 335 wr32(hw, hw->aq.arq.head, 0);
341 wr32(hw, hw->aq.arq.tail, 0); 336 wr32(hw, hw->aq.arq.tail, 0);
342 337
343 if (hw->mac.type == I40E_MAC_VF) { 338 /* set starting point */
344 /* configure the receive queue */ 339 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
345 wr32(hw, I40E_VF_ARQBAH1, 340 I40E_PF_ARQLEN_ARQENABLE_MASK));
346 upper_32_bits(hw->aq.arq.desc_buf.pa)); 341 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
347 wr32(hw, I40E_VF_ARQBAL1, 342 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
348 lower_32_bits(hw->aq.arq.desc_buf.pa));
349 wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
350 I40E_VF_ARQLEN1_ARQENABLE_MASK));
351 reg = rd32(hw, I40E_VF_ARQBAL1);
352 } else {
353 /* configure the receive queue */
354 wr32(hw, I40E_PF_ARQBAH,
355 upper_32_bits(hw->aq.arq.desc_buf.pa));
356 wr32(hw, I40E_PF_ARQBAL,
357 lower_32_bits(hw->aq.arq.desc_buf.pa));
358 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
359 I40E_PF_ARQLEN_ARQENABLE_MASK));
360 reg = rd32(hw, I40E_PF_ARQBAL);
361 }
362 343
363 /* Update tail in the HW to post pre-allocated buffers */ 344 /* Update tail in the HW to post pre-allocated buffers */
364 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); 345 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
365 346
366 /* Check one register to verify that config was applied */ 347 /* Check one register to verify that config was applied */
348 reg = rd32(hw, hw->aq.arq.bal);
367 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) 349 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
368 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 350 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
369 351
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq.h
index e3472c62e155..933537564d95 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq.h
@@ -56,6 +56,8 @@ struct i40e_adminq_ring {
56 u32 head; 56 u32 head;
57 u32 tail; 57 u32 tail;
58 u32 len; 58 u32 len;
59 u32 bah;
60 u32 bal;
59}; 61};
60 62
61/* ASQ transaction details */ 63/* ASQ transaction details */
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-15 14:11:37 -0400