diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-01-14 00:30:40 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-01-21 21:18:04 -0500 |
commit | 87c33f4e9f962f7facab0077f45b2cb21f46d03a (patch) | |
tree | c3a84770c739971ce7a36432085787dc46926d31 | |
parent | 87a876579abd1df8479ad90974492ec0a145d165 (diff) |
drm/nouveau/msvld: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c) | 75 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c) | 73 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c) | 73 |
9 files changed, 141 insertions, 143 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h index f031bb9de74c..1f193b7bd6c5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h | |||
@@ -1,6 +1,7 @@ | |||
1 | #ifndef __NVKM_MSVLD_H__ | 1 | #ifndef __NVKM_MSVLD_H__ |
2 | #define __NVKM_MSVLD_H__ | 2 | #define __NVKM_MSVLD_H__ |
3 | extern struct nouveau_oclass nv98_msvld_oclass; | 3 | #include <core/engine.h> |
4 | extern struct nouveau_oclass nvc0_msvld_oclass; | 4 | extern struct nvkm_oclass g98_msvld_oclass; |
5 | extern struct nouveau_oclass nve0_msvld_oclass; | 5 | extern struct nvkm_oclass gf100_msvld_oclass; |
6 | extern struct nvkm_oclass gk104_msvld_oclass; | ||
6 | #endif | 7 | #endif |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index a5a9c8bf8f0d..4c45f57e81d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | |||
@@ -94,7 +94,7 @@ gm100_identify(struct nouveau_device *device) | |||
94 | #endif | 94 | #endif |
95 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 95 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
96 | #if 0 | 96 | #if 0 |
97 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 97 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
98 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 98 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
99 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 99 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
100 | #endif | 100 | #endif |
@@ -137,7 +137,7 @@ gm100_identify(struct nouveau_device *device) | |||
137 | device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; | 137 | device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; |
138 | device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; | 138 | device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; |
139 | device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; | 139 | device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; |
140 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 140 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
141 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 141 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
142 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 142 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
143 | #endif | 143 | #endif |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index a7838a7c1901..ef87c7ec5812 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | |||
@@ -256,7 +256,7 @@ nv50_identify(struct nouveau_device *device) | |||
256 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; | 256 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
257 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; | 257 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; |
258 | device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; | 258 | device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; |
259 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; | 259 | device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; |
260 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; | 260 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; |
261 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; | 261 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
262 | device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; | 262 | device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; |
@@ -314,7 +314,7 @@ nv50_identify(struct nouveau_device *device) | |||
314 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; | 314 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
315 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; | 315 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; |
316 | device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; | 316 | device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; |
317 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; | 317 | device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; |
318 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; | 318 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; |
319 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; | 319 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
320 | device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; | 320 | device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; |
@@ -343,7 +343,7 @@ nv50_identify(struct nouveau_device *device) | |||
343 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; | 343 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
344 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; | 344 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; |
345 | device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; | 345 | device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; |
346 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; | 346 | device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; |
347 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; | 347 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; |
348 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; | 348 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
349 | device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; | 349 | device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; |
@@ -373,7 +373,7 @@ nv50_identify(struct nouveau_device *device) | |||
373 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; | 373 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
374 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; | 374 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
375 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; | 375 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; |
376 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; | 376 | device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; |
377 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; | 377 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; |
378 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; | 378 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; |
379 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; | 379 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
@@ -403,7 +403,7 @@ nv50_identify(struct nouveau_device *device) | |||
403 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; | 403 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
404 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; | 404 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
405 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; | 405 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; |
406 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; | 406 | device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; |
407 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; | 407 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; |
408 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; | 408 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; |
409 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; | 409 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
@@ -433,7 +433,7 @@ nv50_identify(struct nouveau_device *device) | |||
433 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; | 433 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
434 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; | 434 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
435 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; | 435 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; |
436 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; | 436 | device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; |
437 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; | 437 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; |
438 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; | 438 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; |
439 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; | 439 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
@@ -463,7 +463,7 @@ nv50_identify(struct nouveau_device *device) | |||
463 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; | 463 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
464 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; | 464 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
465 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; | 465 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; |
466 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; | 466 | device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; |
467 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; | 467 | device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; |
468 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; | 468 | device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; |
469 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; | 469 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 83dd982b1c4c..c8ac22e98c87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | |||
@@ -85,7 +85,7 @@ nvc0_identify(struct nouveau_device *device) | |||
85 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 85 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
86 | device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; | 86 | device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; |
87 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 87 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
88 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 88 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
89 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 89 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
90 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 90 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
91 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; | 91 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; |
@@ -118,7 +118,7 @@ nvc0_identify(struct nouveau_device *device) | |||
118 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 118 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
119 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; | 119 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; |
120 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 120 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
121 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 121 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
122 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 122 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
123 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 123 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
124 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; | 124 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; |
@@ -151,7 +151,7 @@ nvc0_identify(struct nouveau_device *device) | |||
151 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 151 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
152 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; | 152 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; |
153 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 153 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
154 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 154 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
155 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 155 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
156 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 156 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
157 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; | 157 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
@@ -183,7 +183,7 @@ nvc0_identify(struct nouveau_device *device) | |||
183 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 183 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
184 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; | 184 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; |
185 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 185 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
186 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 186 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
187 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 187 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
188 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 188 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
189 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; | 189 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; |
@@ -216,7 +216,7 @@ nvc0_identify(struct nouveau_device *device) | |||
216 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 216 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
217 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; | 217 | device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; |
218 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 218 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
219 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 219 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
220 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 220 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
221 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 221 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
222 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; | 222 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
@@ -248,7 +248,7 @@ nvc0_identify(struct nouveau_device *device) | |||
248 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 248 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
249 | device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; | 249 | device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; |
250 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 250 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
251 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 251 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
252 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 252 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
253 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 253 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
254 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; | 254 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
@@ -280,7 +280,7 @@ nvc0_identify(struct nouveau_device *device) | |||
280 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 280 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
281 | device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; | 281 | device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; |
282 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 282 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
283 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 283 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
284 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 284 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
285 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 285 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
286 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; | 286 | device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; |
@@ -313,7 +313,7 @@ nvc0_identify(struct nouveau_device *device) | |||
313 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 313 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
314 | device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; | 314 | device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; |
315 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 315 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
316 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 316 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
317 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 317 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
318 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 318 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
319 | device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; | 319 | device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; |
@@ -343,7 +343,7 @@ nvc0_identify(struct nouveau_device *device) | |||
343 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; | 343 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
344 | device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; | 344 | device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; |
345 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; | 345 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; |
346 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; | 346 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; |
347 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 347 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
348 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; | 348 | device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; |
349 | device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; | 349 | device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 5676a0251c79..d0894674be44 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | |||
@@ -88,7 +88,7 @@ nve0_identify(struct nouveau_device *device) | |||
88 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; | 88 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; |
89 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; | 89 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; |
90 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 90 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
91 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 91 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
92 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 92 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
93 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 93 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
94 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; | 94 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; |
@@ -122,7 +122,7 @@ nve0_identify(struct nouveau_device *device) | |||
122 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; | 122 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; |
123 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; | 123 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; |
124 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 124 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
125 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 125 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
126 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 126 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
127 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 127 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
128 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; | 128 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; |
@@ -156,7 +156,7 @@ nve0_identify(struct nouveau_device *device) | |||
156 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; | 156 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; |
157 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; | 157 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; |
158 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 158 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
159 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 159 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
160 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 160 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
161 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 161 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
162 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; | 162 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; |
@@ -212,7 +212,7 @@ nve0_identify(struct nouveau_device *device) | |||
212 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; | 212 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; |
213 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; | 213 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; |
214 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 214 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
215 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 215 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
216 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 216 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
217 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 217 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
218 | device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; | 218 | device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; |
@@ -246,7 +246,7 @@ nve0_identify(struct nouveau_device *device) | |||
246 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; | 246 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; |
247 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; | 247 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; |
248 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 248 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
249 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 249 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
250 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 250 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
251 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 251 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
252 | device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; | 252 | device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; |
@@ -280,7 +280,7 @@ nve0_identify(struct nouveau_device *device) | |||
280 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; | 280 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; |
281 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; | 281 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; |
282 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 282 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
283 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 283 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
284 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 284 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
285 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 285 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
286 | break; | 286 | break; |
@@ -313,7 +313,7 @@ nve0_identify(struct nouveau_device *device) | |||
313 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; | 313 | device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; |
314 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; | 314 | device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; |
315 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; | 315 | device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; |
316 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; | 316 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; |
317 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | 317 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; |
318 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 318 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
319 | break; | 319 | break; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild index 1deb463a2b0b..0c9811009e28 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild | |||
@@ -1,3 +1,3 @@ | |||
1 | nvkm-y += nvkm/engine/msvld/nv98.o | 1 | nvkm-y += nvkm/engine/msvld/g98.o |
2 | nvkm-y += nvkm/engine/msvld/nvc0.o | 2 | nvkm-y += nvkm/engine/msvld/gf100.o |
3 | nvkm-y += nvkm/engine/msvld/nve0.o | 3 | nvkm-y += nvkm/engine/msvld/gk104.o |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c index 4bafba59226c..c8a6b4ef52a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c | |||
@@ -21,23 +21,22 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin | 22 | * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin |
23 | */ | 23 | */ |
24 | |||
25 | #include <engine/falcon.h> | ||
26 | #include <engine/msvld.h> | 24 | #include <engine/msvld.h> |
25 | #include <engine/falcon.h> | ||
27 | 26 | ||
28 | struct nv98_msvld_priv { | 27 | struct g98_msvld_priv { |
29 | struct nouveau_falcon base; | 28 | struct nvkm_falcon base; |
30 | }; | 29 | }; |
31 | 30 | ||
32 | /******************************************************************************* | 31 | /******************************************************************************* |
33 | * MSVLD object classes | 32 | * MSVLD object classes |
34 | ******************************************************************************/ | 33 | ******************************************************************************/ |
35 | 34 | ||
36 | static struct nouveau_oclass | 35 | static struct nvkm_oclass |
37 | nv98_msvld_sclass[] = { | 36 | g98_msvld_sclass[] = { |
38 | { 0x88b1, &nouveau_object_ofuncs }, | 37 | { 0x88b1, &nvkm_object_ofuncs }, |
39 | { 0x85b1, &nouveau_object_ofuncs }, | 38 | { 0x85b1, &nvkm_object_ofuncs }, |
40 | { 0x86b1, &nouveau_object_ofuncs }, | 39 | { 0x86b1, &nvkm_object_ofuncs }, |
41 | {}, | 40 | {}, |
42 | }; | 41 | }; |
43 | 42 | ||
@@ -45,16 +44,16 @@ nv98_msvld_sclass[] = { | |||
45 | * PMSVLD context | 44 | * PMSVLD context |
46 | ******************************************************************************/ | 45 | ******************************************************************************/ |
47 | 46 | ||
48 | static struct nouveau_oclass | 47 | static struct nvkm_oclass |
49 | nv98_msvld_cclass = { | 48 | g98_msvld_cclass = { |
50 | .handle = NV_ENGCTX(MSVLD, 0x98), | 49 | .handle = NV_ENGCTX(MSVLD, 0x98), |
51 | .ofuncs = &(struct nouveau_ofuncs) { | 50 | .ofuncs = &(struct nvkm_ofuncs) { |
52 | .ctor = _nouveau_falcon_context_ctor, | 51 | .ctor = _nvkm_falcon_context_ctor, |
53 | .dtor = _nouveau_falcon_context_dtor, | 52 | .dtor = _nvkm_falcon_context_dtor, |
54 | .init = _nouveau_falcon_context_init, | 53 | .init = _nvkm_falcon_context_init, |
55 | .fini = _nouveau_falcon_context_fini, | 54 | .fini = _nvkm_falcon_context_fini, |
56 | .rd32 = _nouveau_falcon_context_rd32, | 55 | .rd32 = _nvkm_falcon_context_rd32, |
57 | .wr32 = _nouveau_falcon_context_wr32, | 56 | .wr32 = _nvkm_falcon_context_wr32, |
58 | }, | 57 | }, |
59 | }; | 58 | }; |
60 | 59 | ||
@@ -63,12 +62,12 @@ nv98_msvld_cclass = { | |||
63 | ******************************************************************************/ | 62 | ******************************************************************************/ |
64 | 63 | ||
65 | static int | 64 | static int |
66 | nv98_msvld_init(struct nouveau_object *object) | 65 | g98_msvld_init(struct nvkm_object *object) |
67 | { | 66 | { |
68 | struct nv98_msvld_priv *priv = (void *)object; | 67 | struct g98_msvld_priv *priv = (void *)object; |
69 | int ret; | 68 | int ret; |
70 | 69 | ||
71 | ret = nouveau_falcon_init(&priv->base); | 70 | ret = nvkm_falcon_init(&priv->base); |
72 | if (ret) | 71 | if (ret) |
73 | return ret; | 72 | return ret; |
74 | 73 | ||
@@ -78,34 +77,34 @@ nv98_msvld_init(struct nouveau_object *object) | |||
78 | } | 77 | } |
79 | 78 | ||
80 | static int | 79 | static int |
81 | nv98_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 80 | g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
82 | struct nouveau_oclass *oclass, void *data, u32 size, | 81 | struct nvkm_oclass *oclass, void *data, u32 size, |
83 | struct nouveau_object **pobject) | 82 | struct nvkm_object **pobject) |
84 | { | 83 | { |
85 | struct nv98_msvld_priv *priv; | 84 | struct g98_msvld_priv *priv; |
86 | int ret; | 85 | int ret; |
87 | 86 | ||
88 | ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, | 87 | ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, |
89 | "PMSVLD", "msvld", &priv); | 88 | "PMSVLD", "msvld", &priv); |
90 | *pobject = nv_object(priv); | 89 | *pobject = nv_object(priv); |
91 | if (ret) | 90 | if (ret) |
92 | return ret; | 91 | return ret; |
93 | 92 | ||
94 | nv_subdev(priv)->unit = 0x04008000; | 93 | nv_subdev(priv)->unit = 0x04008000; |
95 | nv_engine(priv)->cclass = &nv98_msvld_cclass; | 94 | nv_engine(priv)->cclass = &g98_msvld_cclass; |
96 | nv_engine(priv)->sclass = nv98_msvld_sclass; | 95 | nv_engine(priv)->sclass = g98_msvld_sclass; |
97 | return 0; | 96 | return 0; |
98 | } | 97 | } |
99 | 98 | ||
100 | struct nouveau_oclass | 99 | struct nvkm_oclass |
101 | nv98_msvld_oclass = { | 100 | g98_msvld_oclass = { |
102 | .handle = NV_ENGINE(MSVLD, 0x98), | 101 | .handle = NV_ENGINE(MSVLD, 0x98), |
103 | .ofuncs = &(struct nouveau_ofuncs) { | 102 | .ofuncs = &(struct nvkm_ofuncs) { |
104 | .ctor = nv98_msvld_ctor, | 103 | .ctor = g98_msvld_ctor, |
105 | .dtor = _nouveau_falcon_dtor, | 104 | .dtor = _nvkm_falcon_dtor, |
106 | .init = nv98_msvld_init, | 105 | .init = g98_msvld_init, |
107 | .fini = _nouveau_falcon_fini, | 106 | .fini = _nvkm_falcon_fini, |
108 | .rd32 = _nouveau_falcon_rd32, | 107 | .rd32 = _nvkm_falcon_rd32, |
109 | .wr32 = _nouveau_falcon_wr32, | 108 | .wr32 = _nvkm_falcon_wr32, |
110 | }, | 109 | }, |
111 | }; | 110 | }; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c index fd2ac0d620c6..b8d1e0f521ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c | |||
@@ -21,21 +21,20 @@ | |||
21 | * | 21 | * |
22 | * Authors: Maarten Lankhorst | 22 | * Authors: Maarten Lankhorst |
23 | */ | 23 | */ |
24 | |||
25 | #include <engine/falcon.h> | ||
26 | #include <engine/msvld.h> | 24 | #include <engine/msvld.h> |
25 | #include <engine/falcon.h> | ||
27 | 26 | ||
28 | struct nvc0_msvld_priv { | 27 | struct gf100_msvld_priv { |
29 | struct nouveau_falcon base; | 28 | struct nvkm_falcon base; |
30 | }; | 29 | }; |
31 | 30 | ||
32 | /******************************************************************************* | 31 | /******************************************************************************* |
33 | * MSVLD object classes | 32 | * MSVLD object classes |
34 | ******************************************************************************/ | 33 | ******************************************************************************/ |
35 | 34 | ||
36 | static struct nouveau_oclass | 35 | static struct nvkm_oclass |
37 | nvc0_msvld_sclass[] = { | 36 | gf100_msvld_sclass[] = { |
38 | { 0x90b1, &nouveau_object_ofuncs }, | 37 | { 0x90b1, &nvkm_object_ofuncs }, |
39 | {}, | 38 | {}, |
40 | }; | 39 | }; |
41 | 40 | ||
@@ -43,16 +42,16 @@ nvc0_msvld_sclass[] = { | |||
43 | * PMSVLD context | 42 | * PMSVLD context |
44 | ******************************************************************************/ | 43 | ******************************************************************************/ |
45 | 44 | ||
46 | static struct nouveau_oclass | 45 | static struct nvkm_oclass |
47 | nvc0_msvld_cclass = { | 46 | gf100_msvld_cclass = { |
48 | .handle = NV_ENGCTX(MSVLD, 0xc0), | 47 | .handle = NV_ENGCTX(MSVLD, 0xc0), |
49 | .ofuncs = &(struct nouveau_ofuncs) { | 48 | .ofuncs = &(struct nvkm_ofuncs) { |
50 | .ctor = _nouveau_falcon_context_ctor, | 49 | .ctor = _nvkm_falcon_context_ctor, |
51 | .dtor = _nouveau_falcon_context_dtor, | 50 | .dtor = _nvkm_falcon_context_dtor, |
52 | .init = _nouveau_falcon_context_init, | 51 | .init = _nvkm_falcon_context_init, |
53 | .fini = _nouveau_falcon_context_fini, | 52 | .fini = _nvkm_falcon_context_fini, |
54 | .rd32 = _nouveau_falcon_context_rd32, | 53 | .rd32 = _nvkm_falcon_context_rd32, |
55 | .wr32 = _nouveau_falcon_context_wr32, | 54 | .wr32 = _nvkm_falcon_context_wr32, |
56 | }, | 55 | }, |
57 | }; | 56 | }; |
58 | 57 | ||
@@ -61,12 +60,12 @@ nvc0_msvld_cclass = { | |||
61 | ******************************************************************************/ | 60 | ******************************************************************************/ |
62 | 61 | ||
63 | static int | 62 | static int |
64 | nvc0_msvld_init(struct nouveau_object *object) | 63 | gf100_msvld_init(struct nvkm_object *object) |
65 | { | 64 | { |
66 | struct nvc0_msvld_priv *priv = (void *)object; | 65 | struct gf100_msvld_priv *priv = (void *)object; |
67 | int ret; | 66 | int ret; |
68 | 67 | ||
69 | ret = nouveau_falcon_init(&priv->base); | 68 | ret = nvkm_falcon_init(&priv->base); |
70 | if (ret) | 69 | if (ret) |
71 | return ret; | 70 | return ret; |
72 | 71 | ||
@@ -76,35 +75,35 @@ nvc0_msvld_init(struct nouveau_object *object) | |||
76 | } | 75 | } |
77 | 76 | ||
78 | static int | 77 | static int |
79 | nvc0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 78 | gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
80 | struct nouveau_oclass *oclass, void *data, u32 size, | 79 | struct nvkm_oclass *oclass, void *data, u32 size, |
81 | struct nouveau_object **pobject) | 80 | struct nvkm_object **pobject) |
82 | { | 81 | { |
83 | struct nvc0_msvld_priv *priv; | 82 | struct gf100_msvld_priv *priv; |
84 | int ret; | 83 | int ret; |
85 | 84 | ||
86 | ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, | 85 | ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, |
87 | "PMSVLD", "msvld", &priv); | 86 | "PMSVLD", "msvld", &priv); |
88 | *pobject = nv_object(priv); | 87 | *pobject = nv_object(priv); |
89 | if (ret) | 88 | if (ret) |
90 | return ret; | 89 | return ret; |
91 | 90 | ||
92 | nv_subdev(priv)->unit = 0x00008000; | 91 | nv_subdev(priv)->unit = 0x00008000; |
93 | nv_subdev(priv)->intr = nouveau_falcon_intr; | 92 | nv_subdev(priv)->intr = nvkm_falcon_intr; |
94 | nv_engine(priv)->cclass = &nvc0_msvld_cclass; | 93 | nv_engine(priv)->cclass = &gf100_msvld_cclass; |
95 | nv_engine(priv)->sclass = nvc0_msvld_sclass; | 94 | nv_engine(priv)->sclass = gf100_msvld_sclass; |
96 | return 0; | 95 | return 0; |
97 | } | 96 | } |
98 | 97 | ||
99 | struct nouveau_oclass | 98 | struct nvkm_oclass |
100 | nvc0_msvld_oclass = { | 99 | gf100_msvld_oclass = { |
101 | .handle = NV_ENGINE(MSVLD, 0xc0), | 100 | .handle = NV_ENGINE(MSVLD, 0xc0), |
102 | .ofuncs = &(struct nouveau_ofuncs) { | 101 | .ofuncs = &(struct nvkm_ofuncs) { |
103 | .ctor = nvc0_msvld_ctor, | 102 | .ctor = gf100_msvld_ctor, |
104 | .dtor = _nouveau_falcon_dtor, | 103 | .dtor = _nvkm_falcon_dtor, |
105 | .init = nvc0_msvld_init, | 104 | .init = gf100_msvld_init, |
106 | .fini = _nouveau_falcon_fini, | 105 | .fini = _nvkm_falcon_fini, |
107 | .rd32 = _nouveau_falcon_rd32, | 106 | .rd32 = _nvkm_falcon_rd32, |
108 | .wr32 = _nouveau_falcon_wr32, | 107 | .wr32 = _nvkm_falcon_wr32, |
109 | }, | 108 | }, |
110 | }; | 109 | }; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c index 4b3d3ca80eff..a0b0927834df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c | |||
@@ -21,21 +21,20 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include <engine/falcon.h> | ||
26 | #include <engine/msvld.h> | 24 | #include <engine/msvld.h> |
25 | #include <engine/falcon.h> | ||
27 | 26 | ||
28 | struct nve0_msvld_priv { | 27 | struct gk104_msvld_priv { |
29 | struct nouveau_falcon base; | 28 | struct nvkm_falcon base; |
30 | }; | 29 | }; |
31 | 30 | ||
32 | /******************************************************************************* | 31 | /******************************************************************************* |
33 | * MSVLD object classes | 32 | * MSVLD object classes |
34 | ******************************************************************************/ | 33 | ******************************************************************************/ |
35 | 34 | ||
36 | static struct nouveau_oclass | 35 | static struct nvkm_oclass |
37 | nve0_msvld_sclass[] = { | 36 | gk104_msvld_sclass[] = { |
38 | { 0x95b1, &nouveau_object_ofuncs }, | 37 | { 0x95b1, &nvkm_object_ofuncs }, |
39 | {}, | 38 | {}, |
40 | }; | 39 | }; |
41 | 40 | ||
@@ -43,16 +42,16 @@ nve0_msvld_sclass[] = { | |||
43 | * PMSVLD context | 42 | * PMSVLD context |
44 | ******************************************************************************/ | 43 | ******************************************************************************/ |
45 | 44 | ||
46 | static struct nouveau_oclass | 45 | static struct nvkm_oclass |
47 | nve0_msvld_cclass = { | 46 | gk104_msvld_cclass = { |
48 | .handle = NV_ENGCTX(MSVLD, 0xe0), | 47 | .handle = NV_ENGCTX(MSVLD, 0xe0), |
49 | .ofuncs = &(struct nouveau_ofuncs) { | 48 | .ofuncs = &(struct nvkm_ofuncs) { |
50 | .ctor = _nouveau_falcon_context_ctor, | 49 | .ctor = _nvkm_falcon_context_ctor, |
51 | .dtor = _nouveau_falcon_context_dtor, | 50 | .dtor = _nvkm_falcon_context_dtor, |
52 | .init = _nouveau_falcon_context_init, | 51 | .init = _nvkm_falcon_context_init, |
53 | .fini = _nouveau_falcon_context_fini, | 52 | .fini = _nvkm_falcon_context_fini, |
54 | .rd32 = _nouveau_falcon_context_rd32, | 53 | .rd32 = _nvkm_falcon_context_rd32, |
55 | .wr32 = _nouveau_falcon_context_wr32, | 54 | .wr32 = _nvkm_falcon_context_wr32, |
56 | }, | 55 | }, |
57 | }; | 56 | }; |
58 | 57 | ||
@@ -61,12 +60,12 @@ nve0_msvld_cclass = { | |||
61 | ******************************************************************************/ | 60 | ******************************************************************************/ |
62 | 61 | ||
63 | static int | 62 | static int |
64 | nve0_msvld_init(struct nouveau_object *object) | 63 | gk104_msvld_init(struct nvkm_object *object) |
65 | { | 64 | { |
66 | struct nve0_msvld_priv *priv = (void *)object; | 65 | struct gk104_msvld_priv *priv = (void *)object; |
67 | int ret; | 66 | int ret; |
68 | 67 | ||
69 | ret = nouveau_falcon_init(&priv->base); | 68 | ret = nvkm_falcon_init(&priv->base); |
70 | if (ret) | 69 | if (ret) |
71 | return ret; | 70 | return ret; |
72 | 71 | ||
@@ -76,35 +75,35 @@ nve0_msvld_init(struct nouveau_object *object) | |||
76 | } | 75 | } |
77 | 76 | ||
78 | static int | 77 | static int |
79 | nve0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 78 | gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
80 | struct nouveau_oclass *oclass, void *data, u32 size, | 79 | struct nvkm_oclass *oclass, void *data, u32 size, |
81 | struct nouveau_object **pobject) | 80 | struct nvkm_object **pobject) |
82 | { | 81 | { |
83 | struct nve0_msvld_priv *priv; | 82 | struct gk104_msvld_priv *priv; |
84 | int ret; | 83 | int ret; |
85 | 84 | ||
86 | ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, | 85 | ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, |
87 | "PMSVLD", "msvld", &priv); | 86 | "PMSVLD", "msvld", &priv); |
88 | *pobject = nv_object(priv); | 87 | *pobject = nv_object(priv); |
89 | if (ret) | 88 | if (ret) |
90 | return ret; | 89 | return ret; |
91 | 90 | ||
92 | nv_subdev(priv)->unit = 0x00008000; | 91 | nv_subdev(priv)->unit = 0x00008000; |
93 | nv_subdev(priv)->intr = nouveau_falcon_intr; | 92 | nv_subdev(priv)->intr = nvkm_falcon_intr; |
94 | nv_engine(priv)->cclass = &nve0_msvld_cclass; | 93 | nv_engine(priv)->cclass = &gk104_msvld_cclass; |
95 | nv_engine(priv)->sclass = nve0_msvld_sclass; | 94 | nv_engine(priv)->sclass = gk104_msvld_sclass; |
96 | return 0; | 95 | return 0; |
97 | } | 96 | } |
98 | 97 | ||
99 | struct nouveau_oclass | 98 | struct nvkm_oclass |
100 | nve0_msvld_oclass = { | 99 | gk104_msvld_oclass = { |
101 | .handle = NV_ENGINE(MSVLD, 0xe0), | 100 | .handle = NV_ENGINE(MSVLD, 0xe0), |
102 | .ofuncs = &(struct nouveau_ofuncs) { | 101 | .ofuncs = &(struct nvkm_ofuncs) { |
103 | .ctor = nve0_msvld_ctor, | 102 | .ctor = gk104_msvld_ctor, |
104 | .dtor = _nouveau_falcon_dtor, | 103 | .dtor = _nvkm_falcon_dtor, |
105 | .init = nve0_msvld_init, | 104 | .init = gk104_msvld_init, |
106 | .fini = _nouveau_falcon_fini, | 105 | .fini = _nvkm_falcon_fini, |
107 | .rd32 = _nouveau_falcon_rd32, | 106 | .rd32 = _nvkm_falcon_rd32, |
108 | .wr32 = _nouveau_falcon_wr32, | 107 | .wr32 = _nvkm_falcon_wr32, |
109 | }, | 108 | }, |
110 | }; | 109 | }; |