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authorArnd Bergmann <arnd@arndb.de>2012-04-25 12:44:23 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-02 12:21:47 -0400
commit878040ef831a12855af26a42cc25c817f4fb3f2d (patch)
tree929921b3d26e7109fdee8b17720d39fc4885b30c
parent8a3fb8607a48ed74db3aaa87d8af7febcaa5d814 (diff)
ARM: bcmring: use proper MMIO accessors
A lot of code in bcmring just dereferences pointers to MMIO locations, which is not safe. This annotates the pointers correctly using __iomem and uses readl/write to access them. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw.c127
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c80
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c11
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/dmacHw.c21
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c2
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h115
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h4
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h2
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw.h2
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h104
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h14
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_io.h6
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/reg.h23
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h10
-rw-r--r--arch/arm/mach-bcmring/include/mach/reg_umi.h2
-rw-r--r--arch/arm/mach-bcmring/mm.c4
-rw-r--r--drivers/mtd/nand/bcm_umi_nand.c12
-rw-r--r--drivers/mtd/nand/nand_bcm_umi.h71
18 files changed, 306 insertions, 304 deletions
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
index 5ac7e2509724..5050833817b7 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom)
61/****************************************************************************/ 61/****************************************************************************/
62chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ 62chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
63 ) { 63 ) {
64 volatile uint32_t *pPLLReg = (uint32_t *) 0x0; 64 uint32_t __iomem *pPLLReg = NULL;
65 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; 65 uint32_t __iomem *pClockCtrl = NULL;
66 volatile uint32_t *pDependentClock = (uint32_t *) 0x0; 66 uint32_t __iomem *pDependentClock = NULL;
67 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ 67 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
68 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ 68 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
69 uint32_t dependentClockType = 0; 69 uint32_t dependentClockType = 0;
70 uint32_t vcoHz = 0; 70 uint32_t vcoHz = 0;
71 71
72 /* Get VCO frequencies */ 72 /* Get VCO frequencies */
73 if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { 73 if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
74 uint64_t adjustFreq = 0; 74 uint64_t adjustFreq = 0;
75 75
76 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * 76 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
77 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * 77 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
78 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> 78 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
79 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); 79 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
80 80
81 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ 81 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur
86 } else { 86 } else {
87 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * 87 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
88 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * 88 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
89 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> 89 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
90 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); 90 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
91 } 91 }
92 vcoFreqPll2Hz = 92 vcoFreqPll2Hz =
93 chipcHw_XTAL_FREQ_Hz * 93 chipcHw_XTAL_FREQ_Hz *
94 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * 94 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
95 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> 95 ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
96 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); 96 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
97 97
98 switch (clock) { 98 switch (clock) {
@@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur
187 187
188 if (pPLLReg) { 188 if (pPLLReg) {
189 /* Obtain PLL clock frequency */ 189 /* Obtain PLL clock frequency */
190 if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { 190 if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
191 /* Return crystal clock frequency when bypassed */ 191 /* Return crystal clock frequency when bypassed */
192 return chipcHw_XTAL_FREQ_Hz; 192 return chipcHw_XTAL_FREQ_Hz;
193 } else if (clock == chipcHw_CLOCK_DDR) { 193 } else if (clock == chipcHw_CLOCK_DDR) {
194 /* DDR frequency is configured in PLLDivider register */ 194 /* DDR frequency is configured in PLLDivider register */
195 return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); 195 return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
196 } else { 196 } else {
197 /* From chip revision number B0, LCD clock is internally divided by 2 */ 197 /* From chip revision number B0, LCD clock is internally divided by 2 */
198 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { 198 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
199 vcoHz >>= 1; 199 vcoHz >>= 1;
200 } 200 }
201 /* Obtain PLL clock frequency using VCO dividers */ 201 /* Obtain PLL clock frequency using VCO dividers */
202 return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); 202 return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
203 } 203 }
204 } else if (pClockCtrl) { 204 } else if (pClockCtrl) {
205 /* Obtain divider clock frequency */ 205 /* Obtain divider clock frequency */
206 uint32_t div; 206 uint32_t div;
207 uint32_t freq = 0; 207 uint32_t freq = 0;
208 208
209 if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { 209 if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
210 /* Return crystal clock frequency when bypassed */ 210 /* Return crystal clock frequency when bypassed */
211 return chipcHw_XTAL_FREQ_Hz; 211 return chipcHw_XTAL_FREQ_Hz;
212 } else if (pDependentClock) { 212 } else if (pDependentClock) {
213 /* Identify the dependent clock frequency */ 213 /* Identify the dependent clock frequency */
214 switch (dependentClockType) { 214 switch (dependentClockType) {
215 case PLL_CLOCK: 215 case PLL_CLOCK:
216 if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { 216 if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
217 /* Use crystal clock frequency when dependent PLL clock is bypassed */ 217 /* Use crystal clock frequency when dependent PLL clock is bypassed */
218 freq = chipcHw_XTAL_FREQ_Hz; 218 freq = chipcHw_XTAL_FREQ_Hz;
219 } else { 219 } else {
220 /* Obtain PLL clock frequency using VCO dividers */ 220 /* Obtain PLL clock frequency using VCO dividers */
221 div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; 221 div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
222 freq = div ? chipcHw_divide(vcoHz, div) : 0; 222 freq = div ? chipcHw_divide(vcoHz, div) : 0;
223 } 223 }
224 break; 224 break;
225 case NON_PLL_CLOCK: 225 case NON_PLL_CLOCK:
226 if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { 226 if (pDependentClock == &pChipcHw->ACLKClock) {
227 freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); 227 freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
228 } else { 228 } else {
229 if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { 229 if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
230 /* Use crystal clock frequency when dependent divider clock is bypassed */ 230 /* Use crystal clock frequency when dependent divider clock is bypassed */
231 freq = chipcHw_XTAL_FREQ_Hz; 231 freq = chipcHw_XTAL_FREQ_Hz;
232 } else { 232 } else {
233 /* Obtain divider clock frequency using XTAL dividers */ 233 /* Obtain divider clock frequency using XTAL dividers */
234 div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; 234 div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
235 freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); 235 freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
236 } 236 }
237 } 237 }
@@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur
242 freq = chipcHw_XTAL_FREQ_Hz; 242 freq = chipcHw_XTAL_FREQ_Hz;
243 } 243 }
244 244
245 div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; 245 div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
246 return chipcHw_divide(freq, (div ? div : 256)); 246 return chipcHw_divide(freq, (div ? div : 256));
247 } 247 }
248 return 0; 248 return 0;
@@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur
261chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ 261chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
262 uint32_t freq /* [ IN ] Clock frequency in Hz */ 262 uint32_t freq /* [ IN ] Clock frequency in Hz */
263 ) { 263 ) {
264 volatile uint32_t *pPLLReg = (uint32_t *) 0x0; 264 uint32_t __iomem *pPLLReg = NULL;
265 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; 265 uint32_t __iomem *pClockCtrl = NULL;
266 volatile uint32_t *pDependentClock = (uint32_t *) 0x0; 266 uint32_t __iomem *pDependentClock = NULL;
267 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ 267 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
268 uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ 268 uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */
269 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ 269 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
@@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
272 uint32_t desVcoHz = 0; 272 uint32_t desVcoHz = 0;
273 273
274 /* Get VCO frequencies */ 274 /* Get VCO frequencies */
275 if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { 275 if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
276 uint64_t adjustFreq = 0; 276 uint64_t adjustFreq = 0;
277 277
278 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * 278 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
279 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * 279 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
280 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> 280 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
281 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); 281 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
282 282
283 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ 283 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
289 /* Desired VCO frequency */ 289 /* Desired VCO frequency */
290 desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * 290 desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
291 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * 291 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
292 (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> 292 (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
293 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); 293 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
294 } else { 294 } else {
295 vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * 295 vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
296 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * 296 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
297 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> 297 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
298 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); 298 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
299 } 299 }
300 vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * 300 vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
301 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> 301 ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
302 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); 302 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
303 303
304 switch (clock) { 304 switch (clock) {
@@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
307 { 307 {
308 REG_LOCAL_IRQ_SAVE; 308 REG_LOCAL_IRQ_SAVE;
309 /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ 309 /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
310 pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) 310 writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
311 << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
312 REG_LOCAL_IRQ_RESTORE; 311 REG_LOCAL_IRQ_RESTORE;
313 } 312 }
314 pPLLReg = &pChipcHw->DDRClock; 313 pPLLReg = &pChipcHw->DDRClock;
@@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
329 /* Configure the VPM:BUS ratio settings */ 328 /* Configure the VPM:BUS ratio settings */
330 { 329 {
331 REG_LOCAL_IRQ_SAVE; 330 REG_LOCAL_IRQ_SAVE;
332 pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) 331 writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
333 << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
334 REG_LOCAL_IRQ_RESTORE; 332 REG_LOCAL_IRQ_RESTORE;
335 } 333 }
336 pPLLReg = &pChipcHw->VPMClock; 334 pPLLReg = &pChipcHw->VPMClock;
@@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
428 /* For DDR settings use only the PLL divider clock */ 426 /* For DDR settings use only the PLL divider clock */
429 if (pPLLReg == &pChipcHw->DDRClock) { 427 if (pPLLReg == &pChipcHw->DDRClock) {
430 /* Set M1DIV for PLL1, which controls the DDR clock */ 428 /* Set M1DIV for PLL1, which controls the DDR clock */
431 reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); 429 reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
432 /* Calculate expected frequency */ 430 /* Calculate expected frequency */
433 freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); 431 freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
434 } else { 432 } else {
435 /* From chip revision number B0, LCD clock is internally divided by 2 */ 433 /* From chip revision number B0, LCD clock is internally divided by 2 */
436 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { 434 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
@@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
441 reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); 439 reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
442 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); 440 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
443 /* Calculate expected frequency */ 441 /* Calculate expected frequency */
444 freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); 442 freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
445 } 443 }
446 /* Wait for for atleast 200ns as per the protocol to change frequency */ 444 /* Wait for for atleast 200ns as per the protocol to change frequency */
447 udelay(1); 445 udelay(1);
@@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
460 if (pDependentClock) { 458 if (pDependentClock) {
461 switch (dependentClockType) { 459 switch (dependentClockType) {
462 case PLL_CLOCK: 460 case PLL_CLOCK:
463 divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); 461 divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
464 break; 462 break;
465 case NON_PLL_CLOCK: 463 case NON_PLL_CLOCK:
466 { 464 {
467 uint32_t sourceClock = 0; 465 uint32_t sourceClock = 0;
468 466
469 if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { 467 if (pDependentClock == &pChipcHw->ACLKClock) {
470 sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); 468 sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
471 } else { 469 } else {
472 uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; 470 uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
473 sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); 471 sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
474 } 472 }
475 divider = chipcHw_divide(sourceClock, freq); 473 divider = chipcHw_divide(sourceClock, freq);
@@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu
483 if (divider) { 481 if (divider) {
484 REG_LOCAL_IRQ_SAVE; 482 REG_LOCAL_IRQ_SAVE;
485 /* Set the divider to obtain the required frequency */ 483 /* Set the divider to obtain the required frequency */
486 *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); 484 writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
487 REG_LOCAL_IRQ_RESTORE; 485 REG_LOCAL_IRQ_RESTORE;
488 return freq; 486 return freq;
489 } 487 }
@@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void)
515 int count = 0; 513 int count = 0;
516 514
517 for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { 515 for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
518 phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; 516 phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
519 phaseValue = 0; 517 phaseValue = 0;
520 prevPhaseComp = 0; 518 prevPhaseComp = 0;
521 519
522 /* Step 1: Look for falling PH_COMP transition */ 520 /* Step 1: Look for falling PH_COMP transition */
523 521
524 /* Read the contents of VPM Clock resgister */ 522 /* Read the contents of VPM Clock resgister */
525 phaseValue = pChipcHw->VPMClock; 523 phaseValue = readl(&pChipcHw->VPMClock);
526 do { 524 do {
527 /* Store previous value of phase comparator */ 525 /* Store previous value of phase comparator */
528 prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; 526 prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
529 /* Change the value of PH_CTRL. */ 527 /* Change the value of PH_CTRL. */
530 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); 528 reg32_write(&pChipcHw->VPMClock,
529 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
531 /* Wait atleast 20 ns */ 530 /* Wait atleast 20 ns */
532 udelay(1); 531 udelay(1);
533 /* Toggle the LOAD_CH after phase control is written. */ 532 /* Toggle the LOAD_CH after phase control is written. */
534 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; 533 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
535 /* Read the contents of VPM Clock resgister. */ 534 /* Read the contents of VPM Clock resgister. */
536 phaseValue = pChipcHw->VPMClock; 535 phaseValue = readl(&pChipcHw->VPMClock);
537 536
538 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { 537 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
539 phaseControl = (0x3F & (phaseControl - 1)); 538 phaseControl = (0x3F & (phaseControl - 1));
@@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void)
557 556
558 for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { 557 for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
559 phaseControl = (0x3F & (phaseControl + 1)); 558 phaseControl = (0x3F & (phaseControl + 1));
560 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); 559 reg32_write(&pChipcHw->VPMClock,
560 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
561 /* Wait atleast 20 ns */ 561 /* Wait atleast 20 ns */
562 udelay(1); 562 udelay(1);
563 /* Toggle the LOAD_CH after phase control is written. */ 563 /* Toggle the LOAD_CH after phase control is written. */
564 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; 564 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
565 phaseValue = pChipcHw->VPMClock; 565 phaseValue = readl(&pChipcHw->VPMClock);
566 /* Count number of adjustment made */ 566 /* Count number of adjustment made */
567 adjustCount++; 567 adjustCount++;
568 } 568 }
@@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void)
581 581
582 for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { 582 for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
583 phaseControl = (0x3F & (phaseControl - 1)); 583 phaseControl = (0x3F & (phaseControl - 1));
584 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); 584 reg32_write(&pChipcHw->VPMClock,
585 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
585 /* Wait atleast 20 ns */ 586 /* Wait atleast 20 ns */
586 udelay(1); 587 udelay(1);
587 /* Toggle the LOAD_CH after phase control is written. */ 588 /* Toggle the LOAD_CH after phase control is written. */
588 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; 589 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
589 phaseValue = pChipcHw->VPMClock; 590 phaseValue = readl(&pChipcHw->VPMClock);
590 /* Count number of adjustment made */ 591 /* Count number of adjustment made */
591 adjustCount++; 592 adjustCount++;
592 } 593 }
@@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void)
605 606
606 for (count = 0; (count < 5); count++) { 607 for (count = 0; (count < 5); count++) {
607 phaseControl = (0x3F & (phaseControl - 1)); 608 phaseControl = (0x3F & (phaseControl - 1));
608 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); 609 reg32_write(&pChipcHw->VPMClock,
610 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
609 /* Wait atleast 20 ns */ 611 /* Wait atleast 20 ns */
610 udelay(1); 612 udelay(1);
611 /* Toggle the LOAD_CH after phase control is written. */ 613 /* Toggle the LOAD_CH after phase control is written. */
612 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; 614 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
613 phaseValue = pChipcHw->VPMClock; 615 phaseValue = readl(&pChipcHw->VPMClock);
614 /* Count number of adjustment made */ 616 /* Count number of adjustment made */
615 adjustCount++; 617 adjustCount++;
616 } 618 }
@@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void)
631 /* Store previous value of phase comparator */ 633 /* Store previous value of phase comparator */
632 prevPhaseComp = phaseValue; 634 prevPhaseComp = phaseValue;
633 /* Change the value of PH_CTRL. */ 635 /* Change the value of PH_CTRL. */
634 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); 636 reg32_write(&pChipcHw->VPMClock,
637 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
635 /* Wait atleast 20 ns */ 638 /* Wait atleast 20 ns */
636 udelay(1); 639 udelay(1);
637 /* Toggle the LOAD_CH after phase control is written. */ 640 /* Toggle the LOAD_CH after phase control is written. */
638 pChipcHw->VPMClock ^= 641 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
639 chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
640 /* Read the contents of VPM Clock resgister. */ 642 /* Read the contents of VPM Clock resgister. */
641 phaseValue = pChipcHw->VPMClock; 643 phaseValue = readl(&pChipcHw->VPMClock);
642 644
643 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { 645 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
644 phaseControl = (0x3F & (phaseControl - 1)); 646 phaseControl = (0x3F & (phaseControl - 1));
@@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void)
661 } 663 }
662 664
663 /* For VPM Phase should be perfectly aligned. */ 665 /* For VPM Phase should be perfectly aligned. */
664 phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); 666 phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
665 { 667 {
666 REG_LOCAL_IRQ_SAVE; 668 REG_LOCAL_IRQ_SAVE;
667 669
668 pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); 670 writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
669 /* Load new phase value */ 671 /* Load new phase value */
670 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; 672 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
671 673
672 REG_LOCAL_IRQ_RESTORE; 674 REG_LOCAL_IRQ_RESTORE;
673 } 675 }
@@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void)
697 int adjustCount = 0; 699 int adjustCount = 0;
698 700
699 /* Disable VPM access */ 701 /* Disable VPM access */
700 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; 702 writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
701 /* Disable HW VPM phase alignment */ 703 /* Disable HW VPM phase alignment */
702 chipcHw_vpmHwPhaseAlignDisable(); 704 chipcHw_vpmHwPhaseAlignDisable();
703 /* Enable SW VPM phase alignment */ 705 /* Enable SW VPM phase alignment */
@@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void)
715 phaseControl--; 717 phaseControl--;
716 } else { 718 } else {
717 /* Enable VPM access */ 719 /* Enable VPM access */
718 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; 720 writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
719 /* Return adjust count */ 721 /* Return adjust count */
720 return adjustCount; 722 return adjustCount;
721 } 723 }
722 /* Change the value of PH_CTRL. */ 724 /* Change the value of PH_CTRL. */
723 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); 725 reg32_write(&pChipcHw->VPMClock,
726 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
724 /* Wait atleast 20 ns */ 727 /* Wait atleast 20 ns */
725 udelay(1); 728 udelay(1);
726 /* Toggle the LOAD_CH after phase control is written. */ 729 /* Toggle the LOAD_CH after phase control is written. */
727 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; 730 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
728 /* Count adjustment */ 731 /* Count adjustment */
729 adjustCount++; 732 adjustCount++;
730 } 733 }
731 } 734 }
732 735
733 /* Disable VPM access */ 736 /* Disable VPM access */
734 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; 737 writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
735 return -1; 738 return -1;
736} 739}
737 740
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
index a711d9bdf318..8377d8054168 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
73 73
74 { 74 {
75 REG_LOCAL_IRQ_SAVE; 75 REG_LOCAL_IRQ_SAVE;
76 pChipcHw->PLLConfig2 = 76 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
77 chipcHw_REG_PLL_CONFIG_D_RESET | 77 chipcHw_REG_PLL_CONFIG_A_RESET,
78 chipcHw_REG_PLL_CONFIG_A_RESET; 78 &pChipcHw->PLLConfig2);
79 79
80 pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | 80 pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
81 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | 81 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
@@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
87 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); 87 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
88 88
89 /* Enable CHIPC registers to control the PLL */ 89 /* Enable CHIPC registers to control the PLL */
90 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; 90 writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
91 91
92 /* Set pre divider to get desired VCO frequency */ 92 /* Set pre divider to get desired VCO frequency */
93 pChipcHw->PLLPreDivider2 = pllPreDivider2; 93 writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
94 /* Set NDIV Frac */ 94 /* Set NDIV Frac */
95 pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; 95 writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
96 96
97 /* This has to be removed once the default values are fixed for PLL2. */ 97 /* This has to be removed once the default values are fixed for PLL2. */
98 pChipcHw->PLLControl12 = 0x38000700; 98 writel(0x38000700, &pChipcHw->PLLControl12);
99 pChipcHw->PLLControl22 = 0x00000015; 99 writel(0x00000015, &pChipcHw->PLLControl22);
100 100
101 /* Reset PLL2 */ 101 /* Reset PLL2 */
102 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { 102 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
103 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | 103 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
104 chipcHw_REG_PLL_CONFIG_A_RESET | 104 chipcHw_REG_PLL_CONFIG_A_RESET |
105 chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | 105 chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
106 chipcHw_REG_PLL_CONFIG_POWER_DOWN; 106 chipcHw_REG_PLL_CONFIG_POWER_DOWN,
107 &pChipcHw->PLLConfig2);
107 } else { 108 } else {
108 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | 109 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
109 chipcHw_REG_PLL_CONFIG_A_RESET | 110 chipcHw_REG_PLL_CONFIG_A_RESET |
110 chipcHw_REG_PLL_CONFIG_VCO_800_1600 | 111 chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
111 chipcHw_REG_PLL_CONFIG_POWER_DOWN; 112 chipcHw_REG_PLL_CONFIG_POWER_DOWN,
113 &pChipcHw->PLLConfig2);
112 } 114 }
113 REG_LOCAL_IRQ_RESTORE; 115 REG_LOCAL_IRQ_RESTORE;
114 } 116 }
@@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
119 { 121 {
120 REG_LOCAL_IRQ_SAVE; 122 REG_LOCAL_IRQ_SAVE;
121 /* Remove analog reset and Power on the PLL */ 123 /* Remove analog reset and Power on the PLL */
122 pChipcHw->PLLConfig2 &= 124 writel(readl(&pChipcHw->PLLConfig2) &
123 ~(chipcHw_REG_PLL_CONFIG_A_RESET | 125 ~(chipcHw_REG_PLL_CONFIG_A_RESET |
124 chipcHw_REG_PLL_CONFIG_POWER_DOWN); 126 chipcHw_REG_PLL_CONFIG_POWER_DOWN),
127 &pChipcHw->PLLConfig2);
125 128
126 REG_LOCAL_IRQ_RESTORE; 129 REG_LOCAL_IRQ_RESTORE;
127 130
128 } 131 }
129 132
130 /* Wait until PLL is locked */ 133 /* Wait until PLL is locked */
131 while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) 134 while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
132 ; 135 ;
133 136
134 { 137 {
135 REG_LOCAL_IRQ_SAVE; 138 REG_LOCAL_IRQ_SAVE;
136 /* Remove digital reset */ 139 /* Remove digital reset */
137 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; 140 writel(readl(&pChipcHw->PLLConfig2) &
141 ~chipcHw_REG_PLL_CONFIG_D_RESET,
142 &pChipcHw->PLLConfig2);
138 143
139 REG_LOCAL_IRQ_RESTORE; 144 REG_LOCAL_IRQ_RESTORE;
140 } 145 }
@@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
157 { 162 {
158 REG_LOCAL_IRQ_SAVE; 163 REG_LOCAL_IRQ_SAVE;
159 164
160 pChipcHw->PLLConfig = 165 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
161 chipcHw_REG_PLL_CONFIG_D_RESET | 166 chipcHw_REG_PLL_CONFIG_A_RESET,
162 chipcHw_REG_PLL_CONFIG_A_RESET; 167 &pChipcHw->PLLConfig);
163 /* Setting VCO frequency */ 168 /* Setting VCO frequency */
164 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { 169 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
165 pllPreDivider = 170 pllPreDivider =
@@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
182 } 187 }
183 188
184 /* Enable CHIPC registers to control the PLL */ 189 /* Enable CHIPC registers to control the PLL */
185 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; 190 writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
186 191
187 /* Set pre divider to get desired VCO frequency */ 192 /* Set pre divider to get desired VCO frequency */
188 pChipcHw->PLLPreDivider = pllPreDivider; 193 writel(pllPreDivider, &pChipcHw->PLLPreDivider);
189 /* Set NDIV Frac */ 194 /* Set NDIV Frac */
190 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { 195 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
191 pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | 196 writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
192 chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
193 } else { 197 } else {
194 pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | 198 writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
195 chipcHw_REG_PLL_DIVIDER_NDIV_f;
196 } 199 }
197 200
198 /* Reset PLL1 */ 201 /* Reset PLL1 */
199 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { 202 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
200 pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | 203 writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
201 chipcHw_REG_PLL_CONFIG_A_RESET |
202 chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
203 chipcHw_REG_PLL_CONFIG_POWER_DOWN;
204 } else { 204 } else {
205 pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | 205 writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
206 chipcHw_REG_PLL_CONFIG_A_RESET |
207 chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
208 chipcHw_REG_PLL_CONFIG_POWER_DOWN;
209 } 206 }
210 207
211 REG_LOCAL_IRQ_RESTORE; 208 REG_LOCAL_IRQ_RESTORE;
@@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
216 { 213 {
217 REG_LOCAL_IRQ_SAVE; 214 REG_LOCAL_IRQ_SAVE;
218 /* Remove analog reset and Power on the PLL */ 215 /* Remove analog reset and Power on the PLL */
219 pChipcHw->PLLConfig &= 216 writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
220 ~(chipcHw_REG_PLL_CONFIG_A_RESET |
221 chipcHw_REG_PLL_CONFIG_POWER_DOWN);
222 REG_LOCAL_IRQ_RESTORE; 217 REG_LOCAL_IRQ_RESTORE;
223 } 218 }
224 219
225 /* Wait until PLL is locked */ 220 /* Wait until PLL is locked */
226 while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) 221 while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
227 || !(pChipcHw-> 222 || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
228 PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
229 ; 223 ;
230 224
231 /* Remove digital reset */ 225 /* Remove digital reset */
232 { 226 {
233 REG_LOCAL_IRQ_SAVE; 227 REG_LOCAL_IRQ_SAVE;
234 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; 228 writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
235 REG_LOCAL_IRQ_RESTORE; 229 REG_LOCAL_IRQ_RESTORE;
236 } 230 }
237 } 231 }
@@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ
267 chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); 261 chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
268 262
269 /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ 263 /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
270 pChipcHw->ACLKClock = 264 writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
271 (pChipcHw->
272 ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
273 armBusRatio &
274 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
275 265
276 /* Set various core component frequencies. The order in which this is done is important for some. */ 266 /* Set various core component frequencies. The order in which this is done is important for some. */
277 /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ 267 /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
index 74d2b023dcec..f95ce913fa1e 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -50,15 +50,16 @@ void chipcHw_reset(uint32_t mask)
50 chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); 50 chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
51 } 51 }
52 /* Bypass the PLL clocks before reboot */ 52 /* Bypass the PLL clocks before reboot */
53 pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; 53 writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
54 pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; 54 &pChipcHw->UARTClock);
55 writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
56 &pChipcHw->SPIClock);
55 57
56 /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ 58 /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
57 do { 59 do {
58 ((uint32_t *) MM_IO_BASE_ARAM)[i] = 60 writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
59 ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
60 i++; 61 i++;
61 } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ 62 } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
62 63
63 flush_cache_all(); 64 flush_cache_all();
64 65
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
index 570ab0ab9232..547f746c7ff4 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -27,7 +27,7 @@
27/* ---- Include Files ---------------------------------------------------- */ 27/* ---- Include Files ---------------------------------------------------- */
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/string.h> 29#include <linux/string.h>
30#include <stddef.h> 30#include <linux/stddef.h>
31 31
32#include <mach/csp/dmacHw.h> 32#include <mach/csp/dmacHw.h>
33#include <mach/csp/dmacHw_reg.h> 33#include <mach/csp/dmacHw_reg.h>
@@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl
55 ) { 55 ) {
56 uint32_t val = 0; 56 uint32_t val = 0;
57 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); 57 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
58 dmacHw_MISC_t *pMiscReg = 58 dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
59 (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
60 59
61 switch (pCblk->channel) { 60 switch (pCblk->channel) {
62 case 0: 61 case 0:
63 val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; 62 val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
64 break; 63 break;
65 case 1: 64 case 1:
66 val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; 65 val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
67 break; 66 break;
68 case 2: 67 case 2:
69 val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; 68 val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
70 break; 69 break;
71 case 3: 70 case 3:
72 val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; 71 val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
73 break; 72 break;
74 case 4: 73 case 4:
75 val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; 74 val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
76 break; 75 break;
77 case 5: 76 case 5:
78 val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; 77 val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
79 break; 78 break;
80 case 6: 79 case 6:
81 val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; 80 val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
82 break; 81 break;
83 case 7: 82 case 7:
84 val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; 83 val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
85 break; 84 break;
86 } 85 }
87 86
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index ea0bd642b364..fe438699d11e 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -27,7 +27,7 @@
27/* ---- Include Files ---------------------------------------------------- */ 27/* ---- Include Files ---------------------------------------------------- */
28 28
29#include <linux/types.h> 29#include <linux/types.h>
30#include <stddef.h> 30#include <linux/stddef.h>
31 31
32#include <mach/csp/dmacHw.h> 32#include <mach/csp/dmacHw.h>
33#include <mach/csp/dmacHw_reg.h> 33#include <mach/csp/dmacHw_reg.h>
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
index 830f323c00cd..a66f3f7abb86 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
47/****************************************************************************/ 47/****************************************************************************/
48static inline uint32_t chipcHw_getChipId(void) 48static inline uint32_t chipcHw_getChipId(void)
49{ 49{
50 return pChipcHw->ChipId; 50 return readl(&pChipcHw->ChipId);
51} 51}
52 52
53/****************************************************************************/ 53/****************************************************************************/
@@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void)
59/****************************************************************************/ 59/****************************************************************************/
60static inline void chipcHw_enableSpreadSpectrum(void) 60static inline void chipcHw_enableSpreadSpectrum(void)
61{ 61{
62 if ((pChipcHw-> 62 if ((readl(&pChipcHw->
63 PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != 63 PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
64 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { 64 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
65 ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = 65 writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
66 (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
67 (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << 66 (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
68 ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); 67 ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
69 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= 68 &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
70 ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; 69 writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
70 ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
71 &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
71 } 72 }
72} 73}
73 74
@@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void)
93/****************************************************************************/ 94/****************************************************************************/
94static inline uint32_t chipcHw_getChipProductId(void) 95static inline uint32_t chipcHw_getChipProductId(void)
95{ 96{
96 return (pChipcHw-> 97 return (readl(&pChipcHw->
97 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> 98 ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
98 chipcHw_REG_CHIPID_BASE_SHIFT; 99 chipcHw_REG_CHIPID_BASE_SHIFT;
99} 100}
100 101
@@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void)
109/****************************************************************************/ 110/****************************************************************************/
110static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) 111static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
111{ 112{
112 return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; 113 return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
113} 114}
114 115
115/****************************************************************************/ 116/****************************************************************************/
@@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
156/****************************************************************************/ 157/****************************************************************************/
157static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) 158static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
158{ 159{
159 return pChipcHw->BusIntfClock; 160 return readl(&pChipcHw->BusIntfClock);
160} 161}
161 162
162/****************************************************************************/ 163/****************************************************************************/
@@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask)
215 216
216 /* Deassert module soft reset */ 217 /* Deassert module soft reset */
217 REG_LOCAL_IRQ_SAVE; 218 REG_LOCAL_IRQ_SAVE;
218 pChipcHw->SoftReset1 ^= ctrl1; 219 writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
219 pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); 220 writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
221 (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
220 REG_LOCAL_IRQ_RESTORE; 222 REG_LOCAL_IRQ_RESTORE;
221} 223}
222 224
@@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
227 uint32_t unhold = 0; 229 uint32_t unhold = 0;
228 230
229 REG_LOCAL_IRQ_SAVE; 231 REG_LOCAL_IRQ_SAVE;
230 pChipcHw->SoftReset1 |= ctrl1; 232 writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
231 /* Mask out unhold request bits */ 233 /* Mask out unhold request bits */
232 pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); 234 writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
235 (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
233 236
234 /* Process unhold requests */ 237 /* Process unhold requests */
235 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { 238 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
@@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
246 249
247 if (unhold) { 250 if (unhold) {
248 /* Make sure unhold request is effective */ 251 /* Make sure unhold request is effective */
249 pChipcHw->SoftReset1 &= ~unhold; 252 writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
250 } 253 }
251 REG_LOCAL_IRQ_RESTORE; 254 REG_LOCAL_IRQ_RESTORE;
252} 255}
@@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask)
307/****************************************************************************/ 310/****************************************************************************/
308static inline uint32_t chipcHw_getStickyBits(void) 311static inline uint32_t chipcHw_getStickyBits(void)
309{ 312{
310 return pChipcHw->Sticky; 313 return readl(&pChipcHw->Sticky);
311} 314}
312 315
313/****************************************************************************/ 316/****************************************************************************/
@@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
328 bits |= chipcHw_REG_STICKY_POR_BROM; 331 bits |= chipcHw_REG_STICKY_POR_BROM;
329 } else { 332 } else {
330 uint32_t sticky; 333 uint32_t sticky;
331 sticky = pChipcHw->Sticky; 334 sticky = readl(pChipcHw->Sticky);
332 335
333 if ((mask & chipcHw_REG_STICKY_BOOT_DONE) 336 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
334 && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { 337 && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
@@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
355 bits |= chipcHw_REG_STICKY_GENERAL_5; 358 bits |= chipcHw_REG_STICKY_GENERAL_5;
356 } 359 }
357 } 360 }
358 pChipcHw->Sticky = bits; 361 writel(bits, pChipcHw->Sticky);
359 REG_LOCAL_IRQ_RESTORE; 362 REG_LOCAL_IRQ_RESTORE;
360} 363}
361 364
@@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
377 (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | 380 (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
378 chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | 381 chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
379 chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { 382 chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
380 uint32_t sticky = pChipcHw->Sticky; 383 uint32_t sticky = readl(&pChipcHw->Sticky);
381 384
382 if ((mask & chipcHw_REG_STICKY_BOOT_DONE) 385 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
383 && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { 386 && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
@@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
410 mask &= ~chipcHw_REG_STICKY_GENERAL_5; 413 mask &= ~chipcHw_REG_STICKY_GENERAL_5;
411 } 414 }
412 } 415 }
413 pChipcHw->Sticky = bits | mask; 416 writel(bits | mask, &pChipcHw->Sticky);
414 REG_LOCAL_IRQ_RESTORE; 417 REG_LOCAL_IRQ_RESTORE;
415} 418}
416 419
@@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
426/****************************************************************************/ 429/****************************************************************************/
427static inline uint32_t chipcHw_getSoftStraps(void) 430static inline uint32_t chipcHw_getSoftStraps(void)
428{ 431{
429 return pChipcHw->SoftStraps; 432 return readl(&pChipcHw->SoftStraps);
430} 433}
431 434
432/****************************************************************************/ 435/****************************************************************************/
@@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
456/****************************************************************************/ 459/****************************************************************************/
457static inline uint32_t chipcHw_getPinStraps(void) 460static inline uint32_t chipcHw_getPinStraps(void)
458{ 461{
459 return pChipcHw->PinStraps; 462 return readl(&pChipcHw->PinStraps);
460} 463}
461 464
462/****************************************************************************/ 465/****************************************************************************/
@@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void)
671/****************************************************************************/ 674/****************************************************************************/
672static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) 675static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
673{ 676{
674 return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & 677 return (readl(chipcHw_REG_GPIO_MUX(pin))) &
675 (chipcHw_REG_GPIO_MUX_MASK << 678 (chipcHw_REG_GPIO_MUX_MASK <<
676 chipcHw_REG_GPIO_MUX_POSITION(pin))) >> 679 chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
677 chipcHw_REG_GPIO_MUX_POSITION(pin); 680 chipcHw_REG_GPIO_MUX_POSITION(pin);
678} 681}
679 682
@@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void)
841static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, 844static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
842 chipcHw_OPTYPE_e type, int mode) 845 chipcHw_OPTYPE_e type, int mode)
843{ 846{
844 volatile uint32_t *pPLLReg = (uint32_t *) 0x0; 847 uint32_t __iomem *pPLLReg = NULL;
845 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; 848 uint32_t __iomem *pClockCtrl = NULL;
846 849
847 switch (clock) { 850 switch (clock) {
848 case chipcHw_CLOCK_DDR: 851 case chipcHw_CLOCK_DDR:
@@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
1071/****************************************************************************/ 1074/****************************************************************************/
1072static inline int chipcHw_isSoftwareStrapsEnable(void) 1075static inline int chipcHw_isSoftwareStrapsEnable(void)
1073{ 1076{
1074 return pChipcHw->SoftStraps & 0x00000001; 1077 return readl(&pChipcHw->SoftStraps) & 0x00000001;
1075} 1078}
1076 1079
1077/****************************************************************************/ 1080/****************************************************************************/
@@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void)
1138/****************************************************************************/ 1141/****************************************************************************/
1139static inline int chipcHw_isPllTestEnable(void) 1142static inline int chipcHw_isPllTestEnable(void)
1140{ 1143{
1141 return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; 1144 return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1142} 1145}
1143 1146
1144/****************************************************************************/ 1147/****************************************************************************/
@@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void)
1147/****************************************************************************/ 1150/****************************************************************************/
1148static inline int chipcHw_isPll2TestEnable(void) 1151static inline int chipcHw_isPll2TestEnable(void)
1149{ 1152{
1150 return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; 1153 return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1151} 1154}
1152 1155
1153/****************************************************************************/ 1156/****************************************************************************/
@@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val)
1183/****************************************************************************/ 1186/****************************************************************************/
1184static inline uint8_t chipcHw_getPllTestSelected(void) 1187static inline uint8_t chipcHw_getPllTestSelected(void)
1185{ 1188{
1186 return (uint8_t) ((pChipcHw-> 1189 return (uint8_t) ((readl(&pChipcHw->
1187 PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) 1190 PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1188 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); 1191 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1189} 1192}
1190 1193
@@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void)
1194/****************************************************************************/ 1197/****************************************************************************/
1195static inline uint8_t chipcHw_getPll2TestSelected(void) 1198static inline uint8_t chipcHw_getPll2TestSelected(void)
1196{ 1199{
1197 return (uint8_t) ((pChipcHw-> 1200 return (uint8_t) ((readl(&pChipcHw->
1198 PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) 1201 PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1199 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); 1202 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1200} 1203}
1201 1204
@@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void)
1208static inline void chipcHw_pll1Disable(void) 1211static inline void chipcHw_pll1Disable(void)
1209{ 1212{
1210 REG_LOCAL_IRQ_SAVE; 1213 REG_LOCAL_IRQ_SAVE;
1211 pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; 1214 writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
1215 &pChipcHw->PLLConfig);
1212 REG_LOCAL_IRQ_RESTORE; 1216 REG_LOCAL_IRQ_RESTORE;
1213} 1217}
1214 1218
@@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void)
1221static inline void chipcHw_pll2Disable(void) 1225static inline void chipcHw_pll2Disable(void)
1222{ 1226{
1223 REG_LOCAL_IRQ_SAVE; 1227 REG_LOCAL_IRQ_SAVE;
1224 pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; 1228 writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
1229 &pChipcHw->PLLConfig2);
1225 REG_LOCAL_IRQ_RESTORE; 1230 REG_LOCAL_IRQ_RESTORE;
1226} 1231}
1227 1232
@@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void)
1233static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) 1238static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
1234{ 1239{
1235 REG_LOCAL_IRQ_SAVE; 1240 REG_LOCAL_IRQ_SAVE;
1236 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; 1241 writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
1242 &pChipcHw->Spare1);
1237 REG_LOCAL_IRQ_RESTORE; 1243 REG_LOCAL_IRQ_RESTORE;
1238} 1244}
1239 1245
@@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
1245static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) 1251static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
1246{ 1252{
1247 REG_LOCAL_IRQ_SAVE; 1253 REG_LOCAL_IRQ_SAVE;
1248 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; 1254 writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
1255 &pChipcHw->Spare1);
1249 REG_LOCAL_IRQ_RESTORE; 1256 REG_LOCAL_IRQ_RESTORE;
1250} 1257}
1251 1258
@@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void)
1333static inline void chipcHw_vpmSwPhaseAlignEnable(void) 1340static inline void chipcHw_vpmSwPhaseAlignEnable(void)
1334{ 1341{
1335 REG_LOCAL_IRQ_SAVE; 1342 REG_LOCAL_IRQ_SAVE;
1336 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; 1343 writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
1344 &pChipcHw->VPMPhaseCtrl1);
1337 REG_LOCAL_IRQ_RESTORE; 1345 REG_LOCAL_IRQ_RESTORE;
1338} 1346}
1339 1347
@@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void)
1372static inline void chipcHw_vpmHwPhaseAlignDisable(void) 1380static inline void chipcHw_vpmHwPhaseAlignDisable(void)
1373{ 1381{
1374 REG_LOCAL_IRQ_SAVE; 1382 REG_LOCAL_IRQ_SAVE;
1375 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; 1383 writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
1384 &pChipcHw->VPMPhaseCtrl1);
1376 REG_LOCAL_IRQ_RESTORE; 1385 REG_LOCAL_IRQ_RESTORE;
1377} 1386}
1378 1387
@@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
1474/****************************************************************************/ 1483/****************************************************************************/
1475static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) 1484static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
1476{ 1485{
1477 return (pChipcHw-> 1486 return (readl(&pChipcHw->
1478 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; 1487 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
1479} 1488}
1480 1489
1481/****************************************************************************/ 1490/****************************************************************************/
@@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
1488/****************************************************************************/ 1497/****************************************************************************/
1489static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) 1498static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
1490{ 1499{
1491 return (pChipcHw-> 1500 return (readl(&pChipcHw->
1492 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; 1501 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
1493} 1502}
1494 1503
1495/****************************************************************************/ 1504/****************************************************************************/
@@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
1500/****************************************************************************/ 1509/****************************************************************************/
1501static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) 1510static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
1502{ 1511{
1503 return (pChipcHw-> 1512 return (readl(&pChipcHw->
1504 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> 1513 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
1505 chipcHw_REG_DDR_PHASE_STATUS_SHIFT; 1514 chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
1506} 1515}
1507 1516
@@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
1513/****************************************************************************/ 1522/****************************************************************************/
1514static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) 1523static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
1515{ 1524{
1516 return (pChipcHw-> 1525 return (readl(&pChipcHw->
1517 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> 1526 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
1518 chipcHw_REG_VPM_PHASE_STATUS_SHIFT; 1527 chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
1519} 1528}
1520 1529
@@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
1526/****************************************************************************/ 1535/****************************************************************************/
1527static inline uint32_t chipcHw_getDdrPhaseControl(void) 1536static inline uint32_t chipcHw_getDdrPhaseControl(void)
1528{ 1537{
1529 return (pChipcHw-> 1538 return (readl(&pChipcHw->
1530 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> 1539 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
1531 chipcHw_REG_DDR_PHASE_CTRL_SHIFT; 1540 chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
1532} 1541}
1533 1542
@@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void)
1539/****************************************************************************/ 1548/****************************************************************************/
1540static inline uint32_t chipcHw_getVpmPhaseControl(void) 1549static inline uint32_t chipcHw_getVpmPhaseControl(void)
1541{ 1550{
1542 return (pChipcHw-> 1551 return (readl(&pChipcHw->
1543 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> 1552 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
1544 chipcHw_REG_VPM_PHASE_CTRL_SHIFT; 1553 chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
1545} 1554}
1546 1555
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
index 76d7531d1e1b..26f5d0e4e1dd 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -131,8 +131,8 @@ typedef struct {
131 uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ 131 uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
132} chipcHw_REG_t; 132} chipcHw_REG_t;
133 133
134#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) 134#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
135#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) 135#define pChipcPhysical (MM_ADDR_IO_CHIPC)
136 136
137#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 137#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000
138#define chipcHw_REG_CHIPID_BASE_SHIFT 12 138#define chipcHw_REG_CHIPID_BASE_SHIFT 12
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
index cabb7dab42ba..39da2c1fdafb 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -416,7 +416,7 @@ extern "C" {
416 } ddrcReg_PHY_ADDR_CTL_REG_t; 416 } ddrcReg_PHY_ADDR_CTL_REG_t;
417 417
418#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 418#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
419#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) 419#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
420 420
421/* @todo These SS definitions are duplicates of ones below */ 421/* @todo These SS definitions are duplicates of ones below */
422 422
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
index bde7faa49e77..9dc90f46a84d 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
@@ -23,7 +23,7 @@
23#ifndef _DMACHW_H 23#ifndef _DMACHW_H
24#define _DMACHW_H 24#define _DMACHW_H
25 25
26#include <stddef.h> 26#include <linux/stddef.h>
27 27
28#include <linux/types.h> 28#include <linux/types.h>
29#include <mach/csp/dmacHw_reg.h> 29#include <mach/csp/dmacHw_reg.h>
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
index 1be9556ba14e..7cd0aafa6f6e 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -121,75 +121,75 @@ typedef struct {
121} dmacHw_MISC_t; 121} dmacHw_MISC_t;
122 122
123/* Base registers */ 123/* Base registers */
124#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ 124#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
125#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ 125#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
126 126
127extern uint32_t dmaChannelCount_0; 127extern uint32_t dmaChannelCount_0;
128extern uint32_t dmaChannelCount_1; 128extern uint32_t dmaChannelCount_1;
129 129
130/* Define channel specific registers */ 130/* Define channel specific registers */
131#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) 131#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
132 132
133/* Raw interrupt status registers */ 133/* Raw interrupt status registers */
134#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) 134#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
135#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) 135#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
136#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) 136#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
137#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) 137#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
138#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) 138#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
139#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) 139#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
140 140
141/* Interrupt status registers */ 141/* Interrupt status registers */
142#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) 142#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
143#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) 143#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
144#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) 144#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
145#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) 145#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
146#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) 146#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
147#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) 147#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
148 148
149/* Interrupt status registers */ 149/* Interrupt status registers */
150#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) 150#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
151#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) 151#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
152#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) 152#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
153#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) 153#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
154#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) 154#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
155#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) 155#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
156 156
157/* Interrupt clear registers */ 157/* Interrupt clear registers */
158#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) 158#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
159#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) 159#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
160#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) 160#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
161#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) 161#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
162#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) 162#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
163#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) 163#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
164#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) 164#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
165 165
166/* Software handshaking registers */ 166/* Software handshaking registers */
167#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) 167#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
168#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) 168#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
169#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) 169#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
170#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) 170#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
171#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) 171#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
172#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) 172#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
173#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) 173#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
174 174
175/* Miscellaneous registers */ 175/* Miscellaneous registers */
176#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) 176#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
177#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) 177#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
178#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) 178#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
179#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) 179#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
180#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) 180#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
181#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) 181#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
182#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) 182#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
183#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) 183#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
184#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) 184#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
185#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) 185#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
186#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) 186#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
187#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) 187#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
188#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) 188#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
189#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) 189#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
190#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) 190#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
191#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) 191#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
192#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) 192#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
193 193
194/* Channel control registers */ 194/* Channel control registers */
195#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) 195#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
index 49403d5725e8..f59db25b5632 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -37,9 +37,9 @@
37#define INTCHW_NUM_INTC 3 37#define INTCHW_NUM_INTC 3
38 38
39/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ 39/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
40#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) 40#define INTCHW_INTC0 (MM_IO_BASE_INTC0)
41#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) 41#define INTCHW_INTC1 (MM_IO_BASE_INTC1)
42#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) 42#define INTCHW_SINTC (MM_IO_BASE_SINTC)
43 43
44/* INTC0 - interrupt controller 0 */ 44/* INTC0 - interrupt controller 0 */
45#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ 45#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
@@ -232,15 +232,15 @@
232/* ---- Public Variable Externs ------------------------------------------ */ 232/* ---- Public Variable Externs ------------------------------------------ */
233/* ---- Public Function Prototypes --------------------------------------- */ 233/* ---- Public Function Prototypes --------------------------------------- */
234/* Clear one or more IRQ interrupts. */ 234/* Clear one or more IRQ interrupts. */
235static inline void intcHw_irq_disable(void *basep, uint32_t mask) 235static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
236{ 236{
237 __REG32(basep + INTCHW_INTENCLEAR) = mask; 237 writel(mask, basep + INTCHW_INTENCLEAR);
238} 238}
239 239
240/* Enables one or more IRQ interrupts. */ 240/* Enables one or more IRQ interrupts. */
241static inline void intcHw_irq_enable(void *basep, uint32_t mask) 241static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
242{ 242{
243 __REG32(basep + INTCHW_INTENABLE) = mask; 243 writel(mask, basep + INTCHW_INTENABLE);
244} 244}
245 245
246#endif /* _INTCHW_REG_H */ 246#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
index dbc98ddaeb67..47450c23685a 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -49,7 +49,7 @@
49#ifdef __ASSEMBLY__ 49#ifdef __ASSEMBLY__
50#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) 50#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
51#else 51#else
52#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ 52#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
53 (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) 53 (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
54#endif 54#endif
55#endif 55#endif
@@ -60,8 +60,8 @@
60#ifdef __ASSEMBLY__ 60#ifdef __ASSEMBLY__
61#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) 61#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
62#else 62#else
63#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ 63#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
64 ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) 64 ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
65#endif 65#endif
66#endif 66#endif
67 67
diff --git a/arch/arm/mach-bcmring/include/mach/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h
index 026eb0b3ba2d..d9cbdca8cd25 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/reg.h
@@ -26,12 +26,13 @@
26/* ---- Include Files ---------------------------------------------------- */ 26/* ---- Include Files ---------------------------------------------------- */
27 27
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/io.h>
29 30
30/* ---- Public Constants and Types --------------------------------------- */ 31/* ---- Public Constants and Types --------------------------------------- */
31 32
32#define __REG32(x) (*((volatile uint32_t *)(x))) 33#define __REG32(x) (*((volatile uint32_t __iomem *)(x)))
33#define __REG16(x) (*((volatile uint16_t *)(x))) 34#define __REG16(x) (*((volatile uint16_t __iomem *)(x)))
34#define __REG8(x) (*((volatile uint8_t *) (x))) 35#define __REG8(x) (*((volatile uint8_t __iomem *) (x)))
35 36
36/* Macros used to define a sequence of reserved registers. The start / end */ 37/* Macros used to define a sequence of reserved registers. The start / end */
37/* are byte offsets in the particular register definition, with the "end" */ 38/* are byte offsets in the particular register definition, with the "end" */
@@ -84,31 +85,31 @@
84 85
85#endif 86#endif
86 87
87static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) 88static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
88{ 89{
89 REG_LOCAL_IRQ_SAVE; 90 REG_LOCAL_IRQ_SAVE;
90 *reg &= value; 91 __raw_writel(__raw_readl(reg) & value, reg);
91 REG_LOCAL_IRQ_RESTORE; 92 REG_LOCAL_IRQ_RESTORE;
92} 93}
93 94
94static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) 95static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
95{ 96{
96 REG_LOCAL_IRQ_SAVE; 97 REG_LOCAL_IRQ_SAVE;
97 *reg |= value; 98 __raw_writel(__raw_readl(reg) | value, reg);
98 REG_LOCAL_IRQ_RESTORE; 99 REG_LOCAL_IRQ_RESTORE;
99} 100}
100 101
101static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, 102static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
102 uint32_t value) 103 uint32_t value)
103{ 104{
104 REG_LOCAL_IRQ_SAVE; 105 REG_LOCAL_IRQ_SAVE;
105 *reg = (*reg & mask) | value; 106 __raw_writel((__raw_readl(reg) & mask) | value, reg);
106 REG_LOCAL_IRQ_RESTORE; 107 REG_LOCAL_IRQ_RESTORE;
107} 108}
108 109
109static inline void reg32_write(volatile uint32_t *reg, uint32_t value) 110static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
110{ 111{
111 *reg = value; 112 __raw_writel(value, reg);
112} 113}
113 114
114#endif /* CSP_REG_H */ 115#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
index 9cd6a032ab71..55d3cd4fd1e7 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -34,7 +34,7 @@
34/****************************************************************************/ 34/****************************************************************************/
35static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ 35static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
36 ) { 36 ) {
37 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; 37 secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
38 38
39 if (mask & 0x0000FFFF) { 39 if (mask & 0x0000FFFF) {
40 regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; 40 regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
@@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK
53/****************************************************************************/ 53/****************************************************************************/
54static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ 54static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
55 ) { 55 ) {
56 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; 56 secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
57 57
58 if (mask & 0x0000FFFF) { 58 if (mask & 0x0000FFFF) {
59 regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; 59 writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
60 } 60 }
61 if (mask & 0xFFFF0000) { 61 if (mask & 0xFFFF0000) {
62 regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; 62 writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
63 } 63 }
64} 64}
65 65
@@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA
71/****************************************************************************/ 71/****************************************************************************/
72static inline uint32_t secHw_getStatus(void) 72static inline uint32_t secHw_getStatus(void)
73{ 73{
74 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; 74 secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
75 75
76 return (regp->reg[1].status << 16) + regp->reg[0].status; 76 return (regp->reg[1].status << 16) + regp->reg[0].status;
77} 77}
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
index 041a68eb6661..56dd9de7d83f 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -233,5 +233,5 @@
233#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 233#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018
234/* location within a page (512 byte) */ 234/* location within a page (512 byte) */
235#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 235#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0
236#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) 236#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
237#endif 237#endif
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78ec940..33824a81cac4 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -20,12 +20,12 @@
20#include <mach/hardware.h> 20#include <mach/hardware.h>
21#include <mach/csp/mm_io.h> 21#include <mach/csp/mm_io.h>
22 22
23#define IO_DESC(va, sz) { .virtual = va, \ 23#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
24 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ 24 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
25 .length = sz, \ 25 .length = sz, \
26 .type = MT_DEVICE } 26 .type = MT_DEVICE }
27 27
28#define MEM_DESC(va, sz) { .virtual = va, \ 28#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
29 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ 29 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
30 .length = sz, \ 30 .length = sz, \
31 .type = MT_MEMORY } 31 .type = MT_MEMORY }
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index 6908cdde3065..55e7799f4bf3 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
249int bcm_umi_nand_inithw(void) 249int bcm_umi_nand_inithw(void)
250{ 250{
251 /* Configure nand timing parameters */ 251 /* Configure nand timing parameters */
252 REG_UMI_NAND_TCR &= ~0x7ffff; 252 writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
253 REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; 253 writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
254 254
255#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) 255#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
256 /* enable software control of CS */ 256 /* enable software control of CS */
257 REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; 257 writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
258#endif 258#endif
259 259
260 /* keep NAND chip select asserted */ 260 /* keep NAND chip select asserted */
261 REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; 261 writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
262 262
263 REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; 263 writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
264 /* enable writes to flash */ 264 /* enable writes to flash */
265 REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; 265 writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
266 266
267 writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); 267 writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
268 nand_bcm_umi_wait_till_ready(); 268 nand_bcm_umi_wait_till_ready();
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
index a158d5dd9a02..d90186684db8 100644
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
48/* Check in device is ready */ 48/* Check in device is ready */
49static inline int nand_bcm_umi_dev_ready(void) 49static inline int nand_bcm_umi_dev_ready(void)
50{ 50{
51 return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; 51 return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
52} 52}
53 53
54/* Wait until device is ready */ 54/* Wait until device is ready */
@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
62static inline void nand_bcm_umi_hamming_enable_hwecc(void) 62static inline void nand_bcm_umi_hamming_enable_hwecc(void)
63{ 63{
64 /* disable and reset ECC, 512 byte page */ 64 /* disable and reset ECC, 512 byte page */
65 REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | 65 writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
66 REG_UMI_NAND_ECC_CSR_256BYTE); 66 REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
67 /* enable ECC */ 67 /* enable ECC */
68 REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; 68 writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
69 &REG_UMI_NAND_ECC_CSR);
69} 70}
70 71
71#if NAND_ECC_BCH 72#if NAND_ECC_BCH
@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
76static inline void nand_bcm_umi_bch_enable_read_hwecc(void) 77static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
77{ 78{
78 /* disable and reset ECC */ 79 /* disable and reset ECC */
79 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; 80 writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
80 /* Turn on ECC */ 81 /* Turn on ECC */
81 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; 82 writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
82} 83}
83 84
84/* Enable BCH Write ECC */ 85/* Enable BCH Write ECC */
85static inline void nand_bcm_umi_bch_enable_write_hwecc(void) 86static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
86{ 87{
87 /* disable and reset ECC */ 88 /* disable and reset ECC */
88 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; 89 writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
89 /* Turn on ECC */ 90 /* Turn on ECC */
90 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; 91 writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
91} 92}
92 93
93/* Config number of BCH ECC bytes */ 94/* Config number of BCH ECC bytes */
@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
99 uint32_t numBits = numEccBytes * 8; 100 uint32_t numBits = numEccBytes * 8;
100 101
101 /* disable and reset ECC */ 102 /* disable and reset ECC */
102 REG_UMI_BCH_CTRL_STATUS = 103 writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
103 REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | 104 REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
104 REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; 105 &REG_UMI_BCH_CTRL_STATUS);
105 106
106 /* Every correctible bit requires 13 ECC bits */ 107 /* Every correctible bit requires 13 ECC bits */
107 tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); 108 tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
113 kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); 114 kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
114 115
115 /* Write the settings */ 116 /* Write the settings */
116 REG_UMI_BCH_N = nValue; 117 writel(nValue, &REG_UMI_BCH_N);
117 REG_UMI_BCH_T = tValue; 118 writel(tValue, &REG_UMI_BCH_T);
118 REG_UMI_BCH_K = kValue; 119 writel(kValue, &REG_UMI_BCH_K);
119} 120}
120 121
121/* Pause during ECC read calculation to skip bytes in OOB */ 122/* Pause during ECC read calculation to skip bytes in OOB */
122static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) 123static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
123{ 124{
124 REG_UMI_BCH_CTRL_STATUS = 125 writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
125 REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
126 REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
127} 126}
128 127
129/* Resume during ECC read calculation after skipping bytes in OOB */ 128/* Resume during ECC read calculation after skipping bytes in OOB */
130static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) 129static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
131{ 130{
132 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; 131 writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
133} 132}
134 133
135/* Poll read ECC calc to check when hardware completes */ 134/* Poll read ECC calc to check when hardware completes */
@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
139 138
140 do { 139 do {
141 /* wait for ECC to be valid */ 140 /* wait for ECC to be valid */
142 regVal = REG_UMI_BCH_CTRL_STATUS; 141 regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
143 } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); 142 } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
144 143
145 return regVal; 144 return regVal;
@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
149static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) 148static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
150{ 149{
151 /* wait for ECC to be valid */ 150 /* wait for ECC to be valid */
152 while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) 151 while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
153 == 0) 152 == 0)
154 ; 153 ;
155} 154}
@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
170 if (pageSize != NAND_DATA_ACCESS_SIZE) { 169 if (pageSize != NAND_DATA_ACCESS_SIZE) {
171 /* skip BI */ 170 /* skip BI */
172#if defined(__KERNEL__) && !defined(STANDALONE) 171#if defined(__KERNEL__) && !defined(STANDALONE)
173 *oobp++ = REG_NAND_DATA8; 172 *oobp++ = readb(&REG_NAND_DATA8);
174#else 173#else
175 REG_NAND_DATA8; 174 readb(&REG_NAND_DATA8);
176#endif 175#endif
177 numToRead--; 176 numToRead--;
178 } 177 }
@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
180 while (numToRead > numEccBytes) { 179 while (numToRead > numEccBytes) {
181 /* skip free oob region */ 180 /* skip free oob region */
182#if defined(__KERNEL__) && !defined(STANDALONE) 181#if defined(__KERNEL__) && !defined(STANDALONE)
183 *oobp++ = REG_NAND_DATA8; 182 *oobp++ = readb(&REG_NAND_DATA8);
184#else 183#else
185 REG_NAND_DATA8; 184 readb(&REG_NAND_DATA8);
186#endif 185#endif
187 numToRead--; 186 numToRead--;
188 } 187 }
@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
193 192
194 while (numToRead > 11) { 193 while (numToRead > 11) {
195#if defined(__KERNEL__) && !defined(STANDALONE) 194#if defined(__KERNEL__) && !defined(STANDALONE)
196 *oobp = REG_NAND_DATA8; 195 *oobp = readb(&REG_NAND_DATA8);
197 eccCalc[eccPos++] = *oobp; 196 eccCalc[eccPos++] = *oobp;
198 oobp++; 197 oobp++;
199#else 198#else
200 eccCalc[eccPos++] = REG_NAND_DATA8; 199 eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
201#endif 200#endif
202 numToRead--; 201 numToRead--;
203 } 202 }
@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
207 if (numToRead == 11) { 206 if (numToRead == 11) {
208 /* read BI */ 207 /* read BI */
209#if defined(__KERNEL__) && !defined(STANDALONE) 208#if defined(__KERNEL__) && !defined(STANDALONE)
210 *oobp++ = REG_NAND_DATA8; 209 *oobp++ = readb(&REG_NAND_DATA8);
211#else 210#else
212 REG_NAND_DATA8; 211 readb(&REG_NAND_DATA8);
213#endif 212#endif
214 numToRead--; 213 numToRead--;
215 } 214 }
@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
219 nand_bcm_umi_bch_resume_read_ecc_calc(); 218 nand_bcm_umi_bch_resume_read_ecc_calc();
220 while (numToRead) { 219 while (numToRead) {
221#if defined(__KERNEL__) && !defined(STANDALONE) 220#if defined(__KERNEL__) && !defined(STANDALONE)
222 *oobp = REG_NAND_DATA8; 221 *oobp = readb(&REG_NAND_DATA8);
223 eccCalc[eccPos++] = *oobp; 222 eccCalc[eccPos++] = *oobp;
224 oobp++; 223 oobp++;
225#else 224#else
226 eccCalc[eccPos++] = REG_NAND_DATA8; 225 eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
227#endif 226#endif
228 numToRead--; 227 numToRead--;
229 } 228 }
@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
255 if (pageSize == NAND_DATA_ACCESS_SIZE) { 254 if (pageSize == NAND_DATA_ACCESS_SIZE) {
256 /* Now fill in the ECC bytes */ 255 /* Now fill in the ECC bytes */
257 if (numEccBytes >= 13) 256 if (numEccBytes >= 13)
258 eccVal = REG_UMI_BCH_WR_ECC_3; 257 eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
259 258
260 /* Usually we skip CM in oob[0,1] */ 259 /* Usually we skip CM in oob[0,1] */
261 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], 260 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
268 eccVal & 0xff); /* ECC 12 */ 267 eccVal & 0xff); /* ECC 12 */
269 268
270 if (numEccBytes >= 9) 269 if (numEccBytes >= 9)
271 eccVal = REG_UMI_BCH_WR_ECC_2; 270 eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
272 271
273 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], 272 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
274 (eccVal >> 24) & 0xff); /* ECC11 */ 273 (eccVal >> 24) & 0xff); /* ECC11 */
@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
281 280
282 /* Now fill in the ECC bytes */ 281 /* Now fill in the ECC bytes */
283 if (numEccBytes >= 13) 282 if (numEccBytes >= 13)
284 eccVal = REG_UMI_BCH_WR_ECC_3; 283 eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
285 284
286 /* Usually skip CM in oob[1,2] */ 285 /* Usually skip CM in oob[1,2] */
287 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], 286 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
294 eccVal & 0xff); /* ECC12 */ 293 eccVal & 0xff); /* ECC12 */
295 294
296 if (numEccBytes >= 9) 295 if (numEccBytes >= 9)
297 eccVal = REG_UMI_BCH_WR_ECC_2; 296 eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
298 297
299 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], 298 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
300 (eccVal >> 24) & 0xff); /* ECC11 */ 299 (eccVal >> 24) & 0xff); /* ECC11 */
@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
309 eccVal & 0xff); /* ECC8 */ 308 eccVal & 0xff); /* ECC8 */
310 309
311 if (numEccBytes >= 5) 310 if (numEccBytes >= 5)
312 eccVal = REG_UMI_BCH_WR_ECC_1; 311 eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
313 312
314 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], 313 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
315 (eccVal >> 24) & 0xff); /* ECC7 */ 314 (eccVal >> 24) & 0xff); /* ECC7 */
@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
321 eccVal & 0xff); /* ECC4 */ 320 eccVal & 0xff); /* ECC4 */
322 321
323 if (numEccBytes >= 1) 322 if (numEccBytes >= 1)
324 eccVal = REG_UMI_BCH_WR_ECC_0; 323 eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
325 324
326 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], 325 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
327 (eccVal >> 24) & 0xff); /* ECC3 */ 326 (eccVal >> 24) & 0xff); /* ECC3 */
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-10 10:16:56 -0400