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authorEugene Surovegin <ebs@ebshome.net>2005-10-29 15:47:41 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-29 18:06:54 -0400
commit86e7fe705d1b894df0cbb785991c92fa298af8fb (patch)
tree696caeca281ad23941a8a4bfeec96728273b5cb6
parent1b195916dd9111bbaf043d0dcfdc5d6908590c6e (diff)
[PATCH] PPC 4xx EMAC driver: fix VSC8201 PHY initialization
* MII registers must override strap pins * disable "echo" mode to make 10/HDX work (Franz Sirl) Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.c b/drivers/net/ibm_emac/ibm_emac_phy.c
index a27e49cfe43b..67935dd33a65 100644
--- a/drivers/net/ibm_emac/ibm_emac_phy.c
+++ b/drivers/net/ibm_emac/ibm_emac_phy.c
@@ -236,12 +236,16 @@ static struct mii_phy_def genmii_phy_def = {
236}; 236};
237 237
238/* CIS8201 */ 238/* CIS8201 */
239#define MII_CIS8201_10BTCSR 0x16
240#define TENBTCSR_ECHO_DISABLE 0x2000
239#define MII_CIS8201_EPCR 0x17 241#define MII_CIS8201_EPCR 0x17
240#define EPCR_MODE_MASK 0x3000 242#define EPCR_MODE_MASK 0x3000
241#define EPCR_GMII_MODE 0x0000 243#define EPCR_GMII_MODE 0x0000
242#define EPCR_RGMII_MODE 0x1000 244#define EPCR_RGMII_MODE 0x1000
243#define EPCR_TBI_MODE 0x2000 245#define EPCR_TBI_MODE 0x2000
244#define EPCR_RTBI_MODE 0x3000 246#define EPCR_RTBI_MODE 0x3000
247#define MII_CIS8201_ACSR 0x1c
248#define ACSR_PIN_PRIO_SELECT 0x0004
245 249
246static int cis8201_init(struct mii_phy *phy) 250static int cis8201_init(struct mii_phy *phy)
247{ 251{
@@ -269,6 +273,14 @@ static int cis8201_init(struct mii_phy *phy)
269 } 273 }
270 274
271 phy_write(phy, MII_CIS8201_EPCR, epcr); 275 phy_write(phy, MII_CIS8201_EPCR, epcr);
276
277 /* MII regs override strap pins */
278 phy_write(phy, MII_CIS8201_ACSR,
279 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
280
281 /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
282 phy_write(phy, MII_CIS8201_10BTCSR,
283 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
272 284
273 return 0; 285 return 0;
274} 286}