diff options
author | Chanwoo Choi <cw00.choi@samsung.com> | 2015-04-27 07:36:32 -0400 |
---|---|---|
committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-04-29 08:11:35 -0400 |
commit | 85943d7ea5832afd454b7219ec1d8c2498c4fbcc (patch) | |
tree | eeec9d2fea63cc3357385cf7d438c90478034de3 | |
parent | b57c93be79e4061b8878315df2f6a239ad967d50 (diff) |
clk: exynos5433: Fix wrong PMS value of exynos5433_pll_rates
This patch fixes the wrong PMS value of exynos5433_pll_rates table
for {ATLAS|APOLLO|MEM0|MEM1|BUS|MFC|MPHY|G3D|DISP|ISP|_PLL.
- 720 MHz (mdiv=360, pdiv=6, sdiv=1) -> 700 MHz (mdiv=175, pdiv=3, sdiv=1)
- 350 MHz (mdiv=360, pdiv=6, sdiv=2) -> (mdiv=350, pdiv=6, sdiv=2)
- 133 MHz (mdiv=552, pdiv=6, sdiv=4) -> (mdiv=532, pdiv=6, sdiv=4)
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index ec294260ef09..9e04ae2bb4d7 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c | |||
@@ -748,7 +748,7 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = { | |||
748 | PLL_35XX_RATE(825000000U, 275, 4, 1), | 748 | PLL_35XX_RATE(825000000U, 275, 4, 1), |
749 | PLL_35XX_RATE(800000000U, 400, 6, 1), | 749 | PLL_35XX_RATE(800000000U, 400, 6, 1), |
750 | PLL_35XX_RATE(733000000U, 733, 12, 1), | 750 | PLL_35XX_RATE(733000000U, 733, 12, 1), |
751 | PLL_35XX_RATE(700000000U, 360, 6, 1), | 751 | PLL_35XX_RATE(700000000U, 175, 3, 1), |
752 | PLL_35XX_RATE(667000000U, 222, 4, 1), | 752 | PLL_35XX_RATE(667000000U, 222, 4, 1), |
753 | PLL_35XX_RATE(633000000U, 211, 4, 1), | 753 | PLL_35XX_RATE(633000000U, 211, 4, 1), |
754 | PLL_35XX_RATE(600000000U, 500, 5, 2), | 754 | PLL_35XX_RATE(600000000U, 500, 5, 2), |
@@ -760,14 +760,14 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = { | |||
760 | PLL_35XX_RATE(444000000U, 370, 5, 2), | 760 | PLL_35XX_RATE(444000000U, 370, 5, 2), |
761 | PLL_35XX_RATE(420000000U, 350, 5, 2), | 761 | PLL_35XX_RATE(420000000U, 350, 5, 2), |
762 | PLL_35XX_RATE(400000000U, 400, 6, 2), | 762 | PLL_35XX_RATE(400000000U, 400, 6, 2), |
763 | PLL_35XX_RATE(350000000U, 360, 6, 2), | 763 | PLL_35XX_RATE(350000000U, 350, 6, 2), |
764 | PLL_35XX_RATE(333000000U, 222, 4, 2), | 764 | PLL_35XX_RATE(333000000U, 222, 4, 2), |
765 | PLL_35XX_RATE(300000000U, 500, 5, 3), | 765 | PLL_35XX_RATE(300000000U, 500, 5, 3), |
766 | PLL_35XX_RATE(266000000U, 532, 6, 3), | 766 | PLL_35XX_RATE(266000000U, 532, 6, 3), |
767 | PLL_35XX_RATE(200000000U, 400, 6, 3), | 767 | PLL_35XX_RATE(200000000U, 400, 6, 3), |
768 | PLL_35XX_RATE(166000000U, 332, 6, 3), | 768 | PLL_35XX_RATE(166000000U, 332, 6, 3), |
769 | PLL_35XX_RATE(160000000U, 320, 6, 3), | 769 | PLL_35XX_RATE(160000000U, 320, 6, 3), |
770 | PLL_35XX_RATE(133000000U, 552, 6, 4), | 770 | PLL_35XX_RATE(133000000U, 532, 6, 4), |
771 | PLL_35XX_RATE(100000000U, 400, 6, 4), | 771 | PLL_35XX_RATE(100000000U, 400, 6, 4), |
772 | { /* sentinel */ } | 772 | { /* sentinel */ } |
773 | }; | 773 | }; |