diff options
author | Anton Blanchard <anton@samba.org> | 2005-09-06 00:50:48 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-09-06 02:09:20 -0400 |
commit | 8530935d384bef1467ba76e1f4382f0f8b3c899d (patch) | |
tree | c96ed2a5f10da98ed5726fd01c59e58cb09ad7c7 | |
parent | fd5b4377eacac42293b1a349dbb0f9892bf7f74a (diff) |
[PATCH] ppc64: remove CPU_FTR_PMC8
Remove the CPU_FTR_PMC8 feature now we encode the number of PMCs
directly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r-- | arch/ppc64/kernel/cputable.c | 24 | ||||
-rw-r--r-- | include/asm-ppc64/cputable.h | 2 |
2 files changed, 12 insertions, 14 deletions
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c index a20960e47105..25ab72323c58 100644 --- a/arch/ppc64/kernel/cputable.c +++ b/arch/ppc64/kernel/cputable.c | |||
@@ -54,8 +54,7 @@ struct cpu_spec cpu_specs[] = { | |||
54 | .pvr_value = 0x00400000, | 54 | .pvr_value = 0x00400000, |
55 | .cpu_name = "POWER3 (630)", | 55 | .cpu_name = "POWER3 (630)", |
56 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 56 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
57 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | 57 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, |
58 | CPU_FTR_PMC8, | ||
59 | .cpu_user_features = COMMON_USER_PPC64, | 58 | .cpu_user_features = COMMON_USER_PPC64, |
60 | .icache_bsize = 128, | 59 | .icache_bsize = 128, |
61 | .dcache_bsize = 128, | 60 | .dcache_bsize = 128, |
@@ -67,8 +66,7 @@ struct cpu_spec cpu_specs[] = { | |||
67 | .pvr_value = 0x00410000, | 66 | .pvr_value = 0x00410000, |
68 | .cpu_name = "POWER3 (630+)", | 67 | .cpu_name = "POWER3 (630+)", |
69 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 68 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
70 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | 69 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, |
71 | CPU_FTR_PMC8, | ||
72 | .cpu_user_features = COMMON_USER_PPC64, | 70 | .cpu_user_features = COMMON_USER_PPC64, |
73 | .icache_bsize = 128, | 71 | .icache_bsize = 128, |
74 | .dcache_bsize = 128, | 72 | .dcache_bsize = 128, |
@@ -81,7 +79,7 @@ struct cpu_spec cpu_specs[] = { | |||
81 | .cpu_name = "RS64-II (northstar)", | 79 | .cpu_name = "RS64-II (northstar)", |
82 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 80 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
83 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | 81 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | |
84 | CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, | 82 | CPU_FTR_MMCRA | CPU_FTR_CTRL, |
85 | .cpu_user_features = COMMON_USER_PPC64, | 83 | .cpu_user_features = COMMON_USER_PPC64, |
86 | .icache_bsize = 128, | 84 | .icache_bsize = 128, |
87 | .dcache_bsize = 128, | 85 | .dcache_bsize = 128, |
@@ -94,7 +92,7 @@ struct cpu_spec cpu_specs[] = { | |||
94 | .cpu_name = "RS64-III (pulsar)", | 92 | .cpu_name = "RS64-III (pulsar)", |
95 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 93 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
96 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | 94 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | |
97 | CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, | 95 | CPU_FTR_MMCRA | CPU_FTR_CTRL, |
98 | .cpu_user_features = COMMON_USER_PPC64, | 96 | .cpu_user_features = COMMON_USER_PPC64, |
99 | .icache_bsize = 128, | 97 | .icache_bsize = 128, |
100 | .dcache_bsize = 128, | 98 | .dcache_bsize = 128, |
@@ -107,7 +105,7 @@ struct cpu_spec cpu_specs[] = { | |||
107 | .cpu_name = "RS64-III (icestar)", | 105 | .cpu_name = "RS64-III (icestar)", |
108 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 106 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
109 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | 107 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | |
110 | CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, | 108 | CPU_FTR_MMCRA | CPU_FTR_CTRL, |
111 | .cpu_user_features = COMMON_USER_PPC64, | 109 | .cpu_user_features = COMMON_USER_PPC64, |
112 | .icache_bsize = 128, | 110 | .icache_bsize = 128, |
113 | .dcache_bsize = 128, | 111 | .dcache_bsize = 128, |
@@ -120,7 +118,7 @@ struct cpu_spec cpu_specs[] = { | |||
120 | .cpu_name = "RS64-IV (sstar)", | 118 | .cpu_name = "RS64-IV (sstar)", |
121 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 119 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
122 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | 120 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | |
123 | CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, | 121 | CPU_FTR_MMCRA | CPU_FTR_CTRL, |
124 | .cpu_user_features = COMMON_USER_PPC64, | 122 | .cpu_user_features = COMMON_USER_PPC64, |
125 | .icache_bsize = 128, | 123 | .icache_bsize = 128, |
126 | .dcache_bsize = 128, | 124 | .dcache_bsize = 128, |
@@ -133,7 +131,7 @@ struct cpu_spec cpu_specs[] = { | |||
133 | .cpu_name = "POWER4 (gp)", | 131 | .cpu_name = "POWER4 (gp)", |
134 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 132 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
135 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | | 133 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | |
136 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, | 134 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA, |
137 | .cpu_user_features = COMMON_USER_PPC64, | 135 | .cpu_user_features = COMMON_USER_PPC64, |
138 | .icache_bsize = 128, | 136 | .icache_bsize = 128, |
139 | .dcache_bsize = 128, | 137 | .dcache_bsize = 128, |
@@ -146,7 +144,7 @@ struct cpu_spec cpu_specs[] = { | |||
146 | .cpu_name = "POWER4+ (gq)", | 144 | .cpu_name = "POWER4+ (gq)", |
147 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 145 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
148 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | | 146 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | |
149 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, | 147 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA, |
150 | .cpu_user_features = COMMON_USER_PPC64, | 148 | .cpu_user_features = COMMON_USER_PPC64, |
151 | .icache_bsize = 128, | 149 | .icache_bsize = 128, |
152 | .dcache_bsize = 128, | 150 | .dcache_bsize = 128, |
@@ -160,7 +158,7 @@ struct cpu_spec cpu_specs[] = { | |||
160 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 158 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
161 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | | 159 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | |
162 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | | 160 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | |
163 | CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, | 161 | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA, |
164 | .cpu_user_features = COMMON_USER_PPC64 | | 162 | .cpu_user_features = COMMON_USER_PPC64 | |
165 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 163 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
166 | .icache_bsize = 128, | 164 | .icache_bsize = 128, |
@@ -175,7 +173,7 @@ struct cpu_spec cpu_specs[] = { | |||
175 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 173 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
176 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | | 174 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | |
177 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | | 175 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | |
178 | CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, | 176 | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA, |
179 | .cpu_user_features = COMMON_USER_PPC64 | | 177 | .cpu_user_features = COMMON_USER_PPC64 | |
180 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 178 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
181 | .icache_bsize = 128, | 179 | .icache_bsize = 128, |
@@ -190,7 +188,7 @@ struct cpu_spec cpu_specs[] = { | |||
190 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | | 188 | .cpu_features = CPU_FTR_SPLIT_ID_CACHE | |
191 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | | 189 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | |
192 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | | 190 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | |
193 | CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, | 191 | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA, |
194 | .cpu_user_features = COMMON_USER_PPC64 | | 192 | .cpu_user_features = COMMON_USER_PPC64 | |
195 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 193 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
196 | .icache_bsize = 128, | 194 | .icache_bsize = 128, |
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h index 0c8affc657fa..80b907727a79 100644 --- a/include/asm-ppc64/cputable.h +++ b/include/asm-ppc64/cputable.h | |||
@@ -98,7 +98,7 @@ static inline unsigned long cpu_has_feature(unsigned long feature) | |||
98 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000) | 98 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000) |
99 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) | 99 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) |
100 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) | 100 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) |
101 | #define CPU_FTR_PMC8 ASM_CONST(0x0000008000000000) | 101 | /* unused ASM_CONST(0x0000008000000000) */ |
102 | #define CPU_FTR_SMT ASM_CONST(0x0000010000000000) | 102 | #define CPU_FTR_SMT ASM_CONST(0x0000010000000000) |
103 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) | 103 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) |
104 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) | 104 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) |