gma500: introduce some register maps

All the conditional ugly register selection really wants to be
cleaned up. Use a struct describing each pipe and its registers.

This will also let us hide some of the oddments between platforms
for any future merging of bits together. In particular the way the
DPLL and FP registers randomly wander around.

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

5 files changed, 268 insertions, 1 deletions

diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c
index c10f02068d11..ec062e4c3029 100644
--- a/drivers/gpu/drm/gma500/cdv_device.c
+++ b/drivers/gpu/drm/gma500/cdv_device.c
@@ -485,10 +485,63 @@ static void cdv_hotplug_enable(struct drm_device *dev, bool on)
         }       
 }
 
+/* Cedarview */
+static const struct psb_offset cdv_regmap[2] = {
+        {
+                .fp0 = FPA0,
+                .fp1 = FPA1,
+                .cntr = DSPACNTR,
+                .conf = PIPEACONF,
+                .src = PIPEASRC,
+                .dpll = DPLL_A,
+                .htotal = HTOTAL_A,
+                .hblank = HBLANK_A,
+                .hsync = HSYNC_A,
+                .vtotal = VTOTAL_A,
+                .vblank = VBLANK_A,
+                .vsync = VSYNC_A,
+                .stride = DSPASTRIDE,
+                .size = DSPASIZE,
+                .pos = DSPAPOS,
+                .base = DSPABASE,
+                .surf = DSPASURF,
+                .addr = DSPABASE,
+                .status = PIPEASTAT,
+                .linoff = DSPALINOFF,
+                .tileoff = DSPATILEOFF,
+                .palette = PALETTE_A,
+        },
+        {
+                .fp0 = FPB0,
+                .fp1 = FPB1,
+                .cntr = DSPBCNTR,
+                .conf = PIPEBCONF,
+                .src = PIPEBSRC,
+                .dpll = DPLL_B,
+                .htotal = HTOTAL_B,
+                .hblank = HBLANK_B,
+                .hsync = HSYNC_B,
+                .vtotal = VTOTAL_B,
+                .vblank = VBLANK_B,
+                .vsync = VSYNC_B,
+                .stride = DSPBSTRIDE,
+                .size = DSPBSIZE,
+                .pos = DSPBPOS,
+                .base = DSPBBASE,
+                .surf = DSPBSURF,
+                .addr = DSPBBASE,
+                .status = PIPEBSTAT,
+                .linoff = DSPBLINOFF,
+                .tileoff = DSPBTILEOFF,
+                .palette = PALETTE_B,
+        }
+};
+
 static int cdv_chip_setup(struct drm_device *dev)
 {
         struct drm_psb_private *dev_priv = dev->dev_private;
         INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
+        dev_priv->regmap = cdv_regmap;
         cdv_get_core_freq(dev);
         psb_intel_opregion_init(dev);
         psb_intel_init_bios(dev);
diff --git a/drivers/gpu/drm/gma500/mdfld_device.c b/drivers/gpu/drm/gma500/mdfld_device.c
index ef71ed6a22b0..000d316c6afd 100644
--- a/drivers/gpu/drm/gma500/mdfld_device.c
+++ b/drivers/gpu/drm/gma500/mdfld_device.c
@@ -559,6 +559,84 @@ static int mdfld_power_up(struct drm_device *dev)
         return 0;
 }
 
+/* Medfield  */
+static const struct psb_offset mdfld_regmap[3] = {
+        {
+                .fp0 = MRST_FPA0,
+                .fp1 = MRST_FPA1,
+                .cntr = DSPACNTR,
+                .conf = PIPEACONF,
+                .src = PIPEASRC,
+                .dpll = MRST_DPLL_A,
+                .htotal = HTOTAL_A,
+                .hblank = HBLANK_A,
+                .hsync = HSYNC_A,
+                .vtotal = VTOTAL_A,
+                .vblank = VBLANK_A,
+                .vsync = VSYNC_A,
+                .stride = DSPASTRIDE,
+                .size = DSPASIZE,
+                .pos = DSPAPOS,
+                .surf = DSPASURF,
+                .addr = DSPABASE,
+                .status = PIPEASTAT,
+                .linoff = DSPALINOFF,
+                .tileoff = DSPATILEOFF,
+                .palette = PALETTE_A,
+        },
+        {
+                .fp0 = MDFLD_DPLL_DIV0,
+                .cntr = DSPBCNTR,
+                .conf = PIPEBCONF,
+                .src = PIPEBSRC,
+                .dpll = MDFLD_DPLL_B,
+                .htotal = HTOTAL_B,
+                .hblank = HBLANK_B,
+                .hsync = HSYNC_B,
+                .vtotal = VTOTAL_B,
+                .vblank = VBLANK_B,
+                .vsync = VSYNC_B,
+                .stride = DSPBSTRIDE,
+                .size = DSPBSIZE,
+                .pos = DSPBPOS,
+                .surf = DSPBSURF,
+                .addr = DSPBBASE,
+                .status = PIPEBSTAT,
+                .linoff = DSPBLINOFF,
+                .tileoff = DSPBTILEOFF,
+                .palette = PALETTE_B,
+        },
+        {
+                .cntr = DSPCCNTR,
+                .conf = PIPECCONF,
+                .src = PIPECSRC,
+                /* No DPLL_C */
+                .dpll = MRST_DPLL_A,
+                .htotal = HTOTAL_C,
+                .hblank = HBLANK_C,
+                .hsync = HSYNC_C,
+                .vtotal = VTOTAL_C,
+                .vblank = VBLANK_C,
+                .vsync = VSYNC_C,
+                .stride = DSPCSTRIDE,
+                .size = DSPBSIZE,
+                .pos = DSPCPOS,
+                .surf = DSPCSURF,
+                .addr = DSPCBASE,
+                .status = PIPECSTAT,
+                .linoff = DSPCLINOFF,
+                .tileoff = DSPCTILEOFF,
+                .palette = PALETTE_C,
+        },
+};
+
+static int mdfld_chip_setup(struct drm_device *dev)
+{
+        struct drm_psb_private *dev_priv = dev->dev_private;
+        dev_priv->regmap = mdfld_regmap;
+        return mid_chip_setup(dev);
+}
+
 const struct psb_ops mdfld_chip_ops = {
         .name = "mdfld",
         .accel_2d = 0,
@@ -568,7 +646,7 @@ const struct psb_ops mdfld_chip_ops = {
         .hdmi_mask = (1 << 1),
         .sgx_offset = MRST_SGX_OFFSET,
 
-        .chip_setup = mid_chip_setup,
+        .chip_setup = mdfld_chip_setup,
         .crtc_helper = &mdfld_helper_funcs,
         .crtc_funcs = &psb_intel_crtc_funcs,
 
diff --git a/drivers/gpu/drm/gma500/oaktrail_device.c b/drivers/gpu/drm/gma500/oaktrail_device.c
index e0b3d49a619a..3c3c862ef61e 100644
--- a/drivers/gpu/drm/gma500/oaktrail_device.c
+++ b/drivers/gpu/drm/gma500/oaktrail_device.c
@@ -456,11 +456,62 @@ static int oaktrail_power_up(struct drm_device *dev)
         return 0;
 }
 
+/* Oaktrail */
+static const struct psb_offset oaktrail_regmap[2] = {
+        {
+                .fp0 = MRST_FPA0,
+                .fp1 = MRST_FPA1,
+                .cntr = DSPACNTR,
+                .conf = PIPEACONF,
+                .src = PIPEASRC,
+                .dpll = MRST_DPLL_A,
+                .htotal = HTOTAL_A,
+                .hblank = HBLANK_A,
+                .hsync = HSYNC_A,
+                .vtotal = VTOTAL_A,
+                .vblank = VBLANK_A,
+                .vsync = VSYNC_A,
+                .stride = DSPASTRIDE,
+                .size = DSPASIZE,
+                .pos = DSPAPOS,
+                .surf = DSPASURF,
+                .addr = DSPABASE,
+                .status = PIPEASTAT,
+                .linoff = DSPALINOFF,
+                .tileoff = DSPATILEOFF,
+                .palette = PALETTE_A,
+        },
+        {
+                .fp0 = FPB0,
+                .fp1 = FPB1,
+                .cntr = DSPBCNTR,
+                .conf = PIPEBCONF,
+                .src = PIPEBSRC,
+                .dpll = DPLL_B,
+                .htotal = HTOTAL_B,
+                .hblank = HBLANK_B,
+                .hsync = HSYNC_B,
+                .vtotal = VTOTAL_B,
+                .vblank = VBLANK_B,
+                .vsync = VSYNC_B,
+                .stride = DSPBSTRIDE,
+                .size = DSPBSIZE,
+                .pos = DSPBPOS,
+                .surf = DSPBSURF,
+                .addr = DSPBBASE,
+                .status = PIPEBSTAT,
+                .linoff = DSPBLINOFF,
+                .tileoff = DSPBTILEOFF,
+                .palette = PALETTE_B,
+        },
+};
 
 static int oaktrail_chip_setup(struct drm_device *dev)
 {
         struct drm_psb_private *dev_priv = dev->dev_private;
         int ret;
+        
+        dev_priv->regmap = oaktrail_regmap;
 
         ret = mid_chip_setup(dev);
         if (ret < 0)
diff --git a/drivers/gpu/drm/gma500/psb_device.c b/drivers/gpu/drm/gma500/psb_device.c
index e95cddbceb60..651af6768e14 100644
--- a/drivers/gpu/drm/gma500/psb_device.c
+++ b/drivers/gpu/drm/gma500/psb_device.c
@@ -289,8 +289,62 @@ static void psb_get_core_freq(struct drm_device *dev)
         }
 }
 
+/* Poulsbo */
+static const struct psb_offset psb_regmap[2] = {
+        {
+                .fp0 = FPA0,
+                .fp1 = FPA1,
+                .cntr = DSPACNTR,
+                .conf = PIPEACONF,
+                .src = PIPEASRC,
+                .dpll = DPLL_A,
+                .htotal = HTOTAL_A,
+                .hblank = HBLANK_A,
+                .hsync = HSYNC_A,
+                .vtotal = VTOTAL_A,
+                .vblank = VBLANK_A,
+                .vsync = VSYNC_A,
+                .stride = DSPASTRIDE,
+                .size = DSPASIZE,
+                .pos = DSPAPOS,
+                .base = DSPABASE,
+                .surf = DSPASURF,
+                .addr = DSPABASE,
+                .status = PIPEASTAT,
+                .linoff = DSPALINOFF,
+                .tileoff = DSPATILEOFF,
+                .palette = PALETTE_A,
+        },
+        {
+                .fp0 = FPB0,
+                .fp1 = FPB1,
+                .cntr = DSPBCNTR,
+                .conf = PIPEBCONF,
+                .src = PIPEBSRC,
+                .dpll = DPLL_B,
+                .htotal = HTOTAL_B,
+                .hblank = HBLANK_B,
+                .hsync = HSYNC_B,
+                .vtotal = VTOTAL_B,
+                .vblank = VBLANK_B,
+                .vsync = VSYNC_B,
+                .stride = DSPBSTRIDE,
+                .size = DSPBSIZE,
+                .pos = DSPBPOS,
+                .base = DSPBBASE,
+                .surf = DSPBSURF,
+                .addr = DSPBBASE,
+                .status = PIPEBSTAT,
+                .linoff = DSPBLINOFF,
+                .tileoff = DSPBTILEOFF,
+                .palette = PALETTE_B,
+        }
+};
+
 static int psb_chip_setup(struct drm_device *dev)
 {
+        struct drm_psb_private *dev_priv = dev->dev_private;
+        dev_priv->regmap = psb_regmap;
         psb_get_core_freq(dev);
         gma_intel_setup_gmbus(dev);
         psb_intel_opregion_init(dev);
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index e25f9a124796..fd1bc8f6bf97 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -281,6 +281,36 @@ struct intel_gmbus {
 };
 
 /*
+ *      Register offset maps
+ */
+
+struct psb_offset {
+        u32     fp0;
+        u32     fp1;
+        u32     cntr;
+        u32     conf;
+        u32     src;
+        u32     dpll;
+        u32     dpll_md;
+        u32     htotal;
+        u32     hblank;
+        u32     hsync;
+        u32     vtotal;
+        u32     vblank;
+        u32     vsync;
+        u32     stride;
+        u32     size;
+        u32     pos;
+        u32     surf;
+        u32     addr;
+        u32     base;
+        u32     status;
+        u32     linoff;
+        u32     tileoff;
+        u32     palette;
+};
+
+/*
  *      Register save state. This is used to hold the context when the
  *      device is powered off. In the case of Oaktrail this can (but does not
  *      yet) include screen blank. Operations occuring during the save
@@ -424,6 +454,7 @@ struct psb_ops;
 struct drm_psb_private {
         struct drm_device *dev;
         const struct psb_ops *ops;
+        const struct psb_offset *regmap;
         
         struct child_device_config *child_dev;
         int child_dev_num;